Low-jitter phase-locked loop based on pseudo-differential delay elements
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Park, Sin Chong | ko |
| dc.date.accessioned | 2013-03-04T07:39:19Z | - |
| dc.date.available | 2013-03-04T07:39:19Z | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.issued | 2001-05 | - |
| dc.identifier.citation | IEE ELECTRONICS LETTERS, v.37, no.11, pp.669 - 670 | - |
| dc.identifier.uri | http://hdl.handle.net/10203/82029 | - |
| dc.publisher | IEE | - |
| dc.title | Low-jitter phase-locked loop based on pseudo-differential delay elements | - |
| dc.type | Article | - |
| dc.type.rims | ART | - |
| dc.citation.volume | 37 | - |
| dc.citation.issue | 11 | - |
| dc.citation.beginningpage | 669 | - |
| dc.citation.endingpage | 670 | - |
| dc.citation.publicationname | IEE ELECTRONICS LETTERS | - |
| dc.contributor.localauthor | Park, Sin Chong | - |
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