Gate Delay Characteristics of a Sub-30nm MOS Device with Non-Overlapped Source-Drain to Gate Fegion

Abstract

A metal-oxide-semiconductor field-effect transistor (MOSFET) structure with a non-overlapped source-drain to gate region is proposed to overcome the challenges in fabricating sub-50 nm complementary MOS (CMOS) devices. A dual spacer is used to suppress the short-channel effect (SCE) and to reduce the gate delay. A dielectric spacer induces an inversion layer in the non-overlapped region to act as an extended source/drain region because of a fringing gate electric field that acts to suppress the SCE. An oxide spacer is used to reduce the gate overlap capacitance, which effects a reduction of the gate delay. The key device characteristics were investigated by using extensive simulations, and the internal physics and the speed characteristics were studied with a non-overlap distance. Compared to an overlapped structure, the proposed structure shows a good subthreshold slope and the drain-induced barrier lowering (DIBL) characteristics with a small gate delay. If the V-T roll-off and DIBL are to be suppressed and the intrinsic gate delay minimized, optimized dielectric constant is needed. With an optimized dielectric spacer, the non-overlap structure shows a small gate delay and DIBL characteristics at a fixed metallurgical gate length. that are comparable those of the overlapped structure.