DC Field | Value | Language |
---|---|---|
dc.contributor.author | Taesung Kim | ko |
dc.contributor.author | Sung Ho Wang | ko |
dc.contributor.author | Beomsup Kim | ko |
dc.date.accessioned | 2013-03-03T23:23:34Z | - |
dc.date.available | 2013-03-03T23:23:34Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2002-08 | - |
dc.identifier.citation | ELECTRONICS LETTERS, v.38, no.17, pp.950 - 951 | - |
dc.identifier.issn | 0013-5194 | - |
dc.identifier.uri | http://hdl.handle.net/10203/80903 | - |
dc.description.abstract | A delay-locked loop (DLL) architecture capable of incorporating fast locking and low jitter features simultaneously is reported. A test chip was fabricated in a 0.6 mum CMOS process to prove its functionality. The proposed DLL can align the internal clock to the external reference clock within two cycles and maintain its locking state with the aid of feedback operation. | - |
dc.language | English | - |
dc.publisher | Inst Engineering Technology-Iet | - |
dc.title | Fast locking delay-locked loop using initial delay measurement | - |
dc.type | Article | - |
dc.identifier.wosid | 000178055900006 | - |
dc.identifier.scopusid | 2-s2.0-0037102035 | - |
dc.type.rims | ART | - |
dc.citation.volume | 38 | - |
dc.citation.issue | 17 | - |
dc.citation.beginningpage | 950 | - |
dc.citation.endingpage | 951 | - |
dc.citation.publicationname | ELECTRONICS LETTERS | - |
dc.contributor.localauthor | Beomsup Kim | - |
dc.contributor.nonIdAuthor | Taesung Kim | - |
dc.contributor.nonIdAuthor | Sung Ho Wang | - |
dc.type.journalArticle | Article | - |
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