Showing results 1 to 5 of 5
A Network-Centric Hardware/Algorithm Co-Design to Accelerate Distributed Training of Deep Neural Networks Li, Youjie; PARK, JONGSE; Alian, Mohammad; Yuan, Yifan; Qu, Zheng; Pan, Peitian; Wang, Ren; et al, International Symposium on Microarchitecture (MICRO), IEEE/ACM, 2018-10-24 |
AXILOG: ABSTRACTIONS FOR APPROXIMATE HARDWARE DESIGN AND REUSE Mahajan, Divya; Ramkrishnan, Kartik; Jariwala, Rudra; Yazdanbakhsh, Amir; PARK, JONGSE; Thwaites, Bradley; Nagendrakumar, Anandhavel; et al, IEEE MICRO, v.35, no.5, pp.16 - 30, 2015-09 |
From Tensors to FPGAs: Accelerating Deep Learning Sharma, Hardik; PARK, JONGSE; Samynathan, Balavinayagam; Robatmili, Behnam; Mirkhani, Shahrzad; Esmaeilzadeh, Hadi, Hot Chips: Symposium on High Performance Chips, IEEE/ACM, 2018-08-19 |
Mixed-Signal Charge-Domain Acceleration of Deep Neural Networks through Interleaved Bit-Partitioned Arithmetic Ghodrati, Soroush; Sharma, Hardik; Kinzer, Sean; Yazdanbakhsh, Amir; PARK, JONGSE; Kim, Nam Sung; Burger, Doug; et al, International Conference on Parallel Architectures and Compilation Techniques (PACT), ACM SIGARCH,IEEE Computer Society, 2020-10-07 |
Yin-Yang: Programming Abstractions for Cross-Domain Multi-Acceleration Kim, Joon Kyung; Ahn, Byung Hoon; Kinzer, Sean; Ghodrati, Soroush; Mahapatra, Rohan; Yatham, Brahmendra; Wang, Shu-Ting; et al, IEEE MICRO, v.42, no.5, pp.89 - 98, 2022-09 |
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