Low-Jitter Digital Timing Recovery Techniques for CAP-Based VDSL Applications

Abstract

In this paper, a digital timing recovery technique for carrierless amplitude and phase modulation (CAP)-based very-high-speed digital subscriber line (VDSL) applications is presented. A digital spectral line method is proposed for the timing tone extraction. It avoids the bandwidth expansion normally caused by the nonlinear property of the timing tone extraction block, and lowers the required sampling clock frequency. Also, an adaptive loop gain control scheme is proposed to reduce the timing jitter, simultaneously achieving both fast locking and low steady-state jitter. A prototype timing recovery circuit in a 0.35-mum CMOS technology achieves 12.02-ps and 86-ps rms and peak-to-peak jitter, respectively, at 40-MHz operation. This is equivalent to about 0.1% of the symbol rate, and suitable for VDSL applications. The prototype IC consumes about 55 mW with a 3.0-V power supply.