DC Field | Value | Language |
---|---|---|
dc.contributor.author | Asano, K | ko |
dc.contributor.author | Choi, Yang-Kyu | ko |
dc.contributor.author | King, TJ | ko |
dc.contributor.author | Hu, CM | ko |
dc.date.accessioned | 2013-03-03T16:04:45Z | - |
dc.date.available | 2013-03-03T16:04:45Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2001-05 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON ELECTRON DEVICES, v.48, no.5, pp.1004 - 1006 | - |
dc.identifier.issn | 0018-9383 | - |
dc.identifier.uri | http://hdl.handle.net/10203/79358 | - |
dc.description.abstract | We have investigated two process techniques: resist ashing and oxide hard mask trimming. A combination of ashing and trimming produces sub-30-nm MOSFET gate. These techniques require neither specific equipment nor materials, These can be used to fabricate experimental devices with line width beyond the limit of optical lithography or high-throughput e-beam lithography. They provide 25-nm gate pattern with i-line lithography and sub-20-nm pattern with e-beam lithography, A 40-nm gate channel length nMOSFET is demonstrated. | - |
dc.language | English | - |
dc.publisher | IEEE-Inst Electrical Electronics Engineers Inc | - |
dc.title | Patterning sub-30-nm MOSFET gate with i-line lithography | - |
dc.type | Article | - |
dc.identifier.wosid | 000168361000026 | - |
dc.identifier.scopusid | 2-s2.0-0035339687 | - |
dc.type.rims | ART | - |
dc.citation.volume | 48 | - |
dc.citation.issue | 5 | - |
dc.citation.beginningpage | 1004 | - |
dc.citation.endingpage | 1006 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON ELECTRON DEVICES | - |
dc.identifier.doi | 10.1109/16.918251 | - |
dc.contributor.localauthor | Choi, Yang-Kyu | - |
dc.contributor.nonIdAuthor | Asano, K | - |
dc.contributor.nonIdAuthor | King, TJ | - |
dc.contributor.nonIdAuthor | Hu, CM | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordPlus | FABRICATION | - |
dc.subject.keywordPlus | METAL | - |
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