Low power clock generator based on area-reduced interleaved synchronous mirror delay
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Sung K. | ko |
| dc.contributor.author | Yang B.-D. | ko |
| dc.contributor.author | Kim, Lee-Sup | ko |
| dc.date.accessioned | 2013-03-03T11:29:14Z | - |
| dc.date.available | 2013-03-03T11:29:14Z | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.issued | 2002-04 | - |
| dc.identifier.citation | ELECTRONICS LETTERS, v.38, no.9, pp.399 - 400 | - |
| dc.identifier.issn | 0013-5194 | - |
| dc.identifier.uri | http://hdl.handle.net/10203/78486 | - |
| dc.description.abstract | A new interleaved synchronous mirror delay (SMD) is proposed to reduce circuit size. In addition. the proposed interleaved SMD solves the polarity problem with just One extra inverter, Simulation results show that about 30% power reduction and 40% area reduction are achieved in the proposed interleaved SMD. | - |
| dc.language | English | - |
| dc.publisher | IEE-INST ELEC ENG | - |
| dc.title | Low power clock generator based on area-reduced interleaved synchronous mirror delay | - |
| dc.type | Article | - |
| dc.identifier.wosid | 000175537700004 | - |
| dc.identifier.scopusid | 2-s2.0-0036292981 | - |
| dc.type.rims | ART | - |
| dc.citation.volume | 38 | - |
| dc.citation.issue | 9 | - |
| dc.citation.beginningpage | 399 | - |
| dc.citation.endingpage | 400 | - |
| dc.citation.publicationname | ELECTRONICS LETTERS | - |
| dc.contributor.localauthor | Kim, Lee-Sup | - |
| dc.contributor.nonIdAuthor | Sung K. | - |
| dc.contributor.nonIdAuthor | Yang B.-D. | - |
| dc.type.journalArticle | Article | - |
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