DC Field | Value | Language |
---|---|---|
dc.contributor.author | Wang, SH | ko |
dc.contributor.author | Kim, J | ko |
dc.contributor.author | Lee, J | ko |
dc.contributor.author | Nam, HS | ko |
dc.contributor.author | Kim, YG | ko |
dc.contributor.author | Shim, JH | ko |
dc.contributor.author | Ahn, HK | ko |
dc.contributor.author | Kang, S | ko |
dc.contributor.author | Jeong, BH | ko |
dc.contributor.author | Ahn, JH | ko |
dc.contributor.author | Kim, Beom-Sup | ko |
dc.date.accessioned | 2013-03-03T10:02:40Z | - |
dc.date.available | 2013-03-03T10:02:40Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2001-04 | - |
dc.identifier.citation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.36, no.4, pp.648 - 657 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | http://hdl.handle.net/10203/78307 | - |
dc.description.abstract | A quadruple data rate (QDR) synchronous DRAM (SDRAM) interface processing data at 500 Mb/s/pin with a 125-MHz external clock signal is presented. Since the QDR interface has a narrower data timing window, a precise skew control on data signals is required, A salient skew cancellation technique with a shared skew estimator is proposed. The skew cancellation circuit not only reduces the data signal skews on a printed circuit board down to 250 ps, but also aligns the data signals with an external clock signal. The entire interface, fabricated in a 0.35-mum CMOS technology, includes a high-speed data pattern generator and consumes 570 mW of power at 3.0-V supply, The active die area of the chip with the on-chip data pattern generator is 2.4 mm(2). | - |
dc.language | English | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.subject | DRAM | - |
dc.subject | CMOS | - |
dc.title | A 500-Mb/a quadruple data rate SDRAM interface using a skew cancellation technique | - |
dc.type | Article | - |
dc.identifier.wosid | 000167873300009 | - |
dc.identifier.scopusid | 2-s2.0-0035310054 | - |
dc.type.rims | ART | - |
dc.citation.volume | 36 | - |
dc.citation.issue | 4 | - |
dc.citation.beginningpage | 648 | - |
dc.citation.endingpage | 657 | - |
dc.citation.publicationname | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.contributor.localauthor | Kim, Beom-Sup | - |
dc.contributor.nonIdAuthor | Wang, SH | - |
dc.contributor.nonIdAuthor | Kim, J | - |
dc.contributor.nonIdAuthor | Lee, J | - |
dc.contributor.nonIdAuthor | Nam, HS | - |
dc.contributor.nonIdAuthor | Kim, YG | - |
dc.contributor.nonIdAuthor | Shim, JH | - |
dc.contributor.nonIdAuthor | Ahn, HK | - |
dc.contributor.nonIdAuthor | Kang, S | - |
dc.contributor.nonIdAuthor | Jeong, BH | - |
dc.contributor.nonIdAuthor | Ahn, JH | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | data skew | - |
dc.subject.keywordAuthor | DDR | - |
dc.subject.keywordAuthor | DDR-II | - |
dc.subject.keywordAuthor | delay-locked loop | - |
dc.subject.keywordAuthor | DLL | - |
dc.subject.keywordAuthor | phase-locked loop | - |
dc.subject.keywordAuthor | PLL | - |
dc.subject.keywordAuthor | QDR | - |
dc.subject.keywordAuthor | quadruple data rate | - |
dc.subject.keywordAuthor | SDRAM interface | - |
dc.subject.keywordAuthor | skew cancellation | - |
dc.subject.keywordAuthor | synchronization | - |
dc.subject.keywordAuthor | synchronous DRAM | - |
dc.subject.keywordPlus | DRAM | - |
dc.subject.keywordPlus | CMOS | - |
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