A 500-Mb/a quadruple data rate SDRAM interface using a skew cancellation technique

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dc.contributor.authorWang, SHko
dc.contributor.authorKim, Jko
dc.contributor.authorLee, Jko
dc.contributor.authorNam, HSko
dc.contributor.authorKim, YGko
dc.contributor.authorShim, JHko
dc.contributor.authorAhn, HKko
dc.contributor.authorKang, Sko
dc.contributor.authorJeong, BHko
dc.contributor.authorAhn, JHko
dc.contributor.authorKim, Beom-Supko
dc.date.accessioned2013-03-03T10:02:40Z-
dc.date.available2013-03-03T10:02:40Z-
dc.date.created2012-02-06-
dc.date.created2012-02-06-
dc.date.issued2001-04-
dc.identifier.citationIEEE JOURNAL OF SOLID-STATE CIRCUITS, v.36, no.4, pp.648 - 657-
dc.identifier.issn0018-9200-
dc.identifier.urihttp://hdl.handle.net/10203/78307-
dc.description.abstractA quadruple data rate (QDR) synchronous DRAM (SDRAM) interface processing data at 500 Mb/s/pin with a 125-MHz external clock signal is presented. Since the QDR interface has a narrower data timing window, a precise skew control on data signals is required, A salient skew cancellation technique with a shared skew estimator is proposed. The skew cancellation circuit not only reduces the data signal skews on a printed circuit board down to 250 ps, but also aligns the data signals with an external clock signal. The entire interface, fabricated in a 0.35-mum CMOS technology, includes a high-speed data pattern generator and consumes 570 mW of power at 3.0-V supply, The active die area of the chip with the on-chip data pattern generator is 2.4 mm(2).-
dc.languageEnglish-
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.subjectDRAM-
dc.subjectCMOS-
dc.titleA 500-Mb/a quadruple data rate SDRAM interface using a skew cancellation technique-
dc.typeArticle-
dc.identifier.wosid000167873300009-
dc.identifier.scopusid2-s2.0-0035310054-
dc.type.rimsART-
dc.citation.volume36-
dc.citation.issue4-
dc.citation.beginningpage648-
dc.citation.endingpage657-
dc.citation.publicationnameIEEE JOURNAL OF SOLID-STATE CIRCUITS-
dc.contributor.localauthorKim, Beom-Sup-
dc.contributor.nonIdAuthorWang, SH-
dc.contributor.nonIdAuthorKim, J-
dc.contributor.nonIdAuthorLee, J-
dc.contributor.nonIdAuthorNam, HS-
dc.contributor.nonIdAuthorKim, YG-
dc.contributor.nonIdAuthorShim, JH-
dc.contributor.nonIdAuthorAhn, HK-
dc.contributor.nonIdAuthorKang, S-
dc.contributor.nonIdAuthorJeong, BH-
dc.contributor.nonIdAuthorAhn, JH-
dc.type.journalArticleArticle-
dc.subject.keywordAuthordata skew-
dc.subject.keywordAuthorDDR-
dc.subject.keywordAuthorDDR-II-
dc.subject.keywordAuthordelay-locked loop-
dc.subject.keywordAuthorDLL-
dc.subject.keywordAuthorphase-locked loop-
dc.subject.keywordAuthorPLL-
dc.subject.keywordAuthorQDR-
dc.subject.keywordAuthorquadruple data rate-
dc.subject.keywordAuthorSDRAM interface-
dc.subject.keywordAuthorskew cancellation-
dc.subject.keywordAuthorsynchronization-
dc.subject.keywordAuthorsynchronous DRAM-
dc.subject.keywordPlusDRAM-
dc.subject.keywordPlusCMOS-
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