SEWD: A cache architecture to speed up the misaligned instruction prefetch

Abstract

In microprocessors, reducing the cache access delay and the number of pipeline stall is critical to improve the system performance. In this paper, we propose a Separated Word-line Decoding (SEWD) cache to overcome the pipeline stall caused by the misaligned multi-words data or instruction prefetches which are placed over two cliche lines. SEWD cache makes it possible to perform misaligned prefetch as well as aligned prefetch in one clock cycle. This feature is invaluable because the branch target addresses are very often misaligned (Percentage of misalignment in the cache is 8 to 13% for 16-byte caches). 8 Kbyte SEWD cache chip was implemented in 0.8 mu m DLM CMOS process. It consists of 489,000 transistors on a die size of 0.853 x 0.827 cm(2).