DC Field | Value | Language |
---|---|---|
dc.contributor.author | j. j. kim | ko |
dc.contributor.author | s.-b. lee | ko |
dc.contributor.author | t. -s. jung | ko |
dc.contributor.author | c.-h. kim | ko |
dc.contributor.author | s.-i. cho | ko |
dc.contributor.author | b. kim | ko |
dc.date.accessioned | 2013-03-02T17:15:12Z | - |
dc.date.available | 2013-03-02T17:15:12Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2000-10 | - |
dc.identifier.citation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.35, no.10, pp.1430 - 1436 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | http://hdl.handle.net/10203/74649 | - |
dc.description.abstract | This paper presents a salient clock deskewing method with a mixed-mode delay-locked loop (MDLL) for high-speed synchronous DRAM applications. The presented method not only solves the resolution problem of conventional digital deskewing circuits, but also improves the jitter performance to the le, el of well-designed analog deskewing circuits, while keeping the power consumption and locking speed of digital deskewing circuits. The whole deskewing circuit is fabricated in a 3.3-V 0.6-mu m triple-metal CMOS process and occupies a die area of 0.45 mm(2), Measured rms jitter is 6.38 ps, The power consumption of the entire chip, including I/O peripherals, is 33 mW at 200 MHz with a 3.3-V supply. | - |
dc.language | English | - |
dc.publisher | IEEE-Inst Electrical Electronics Engineers Inc | - |
dc.title | A Low-Jitter Mixed-Mode DLL for Hign-Speed DRAM Applications | - |
dc.type | Article | - |
dc.identifier.wosid | 000089778400007 | - |
dc.identifier.scopusid | 2-s2.0-0034296002 | - |
dc.type.rims | ART | - |
dc.citation.volume | 35 | - |
dc.citation.issue | 10 | - |
dc.citation.beginningpage | 1430 | - |
dc.citation.endingpage | 1436 | - |
dc.citation.publicationname | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.contributor.localauthor | b. kim | - |
dc.contributor.nonIdAuthor | j. j. kim | - |
dc.contributor.nonIdAuthor | s.-b. lee | - |
dc.contributor.nonIdAuthor | t. -s. jung | - |
dc.contributor.nonIdAuthor | c.-h. kim | - |
dc.contributor.nonIdAuthor | s.-i. cho | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | behavior analysis | - |
dc.subject.keywordAuthor | delay-locked loop | - |
dc.subject.keywordAuthor | deskewing | - |
dc.subject.keywordAuthor | jitter | - |
dc.subject.keywordAuthor | jitter analysis | - |
dc.subject.keywordAuthor | locking | - |
dc.subject.keywordAuthor | mixed-mode | - |
dc.subject.keywordAuthor | resolution | - |
dc.subject.keywordAuthor | synchronous DRAM | - |
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