Giga Bit급 저전력 Synchronous DRAM 구조에 대한 연구A Study on the Low Power Architecture of Multi-giga bit Synchronous DRAM's

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dc.contributor.author유회준ko
dc.contributor.author이장우ko
dc.date.accessioned2013-03-02T15:25:56Z-
dc.date.available2013-03-02T15:25:56Z-
dc.date.created2012-02-06-
dc.date.created2012-02-06-
dc.date.issued1997-11-
dc.identifier.citation대한전자공학회 논문지, v.34C, no.11, pp.1 - 11-
dc.identifier.issn1226-5853-
dc.identifier.urihttp://hdl.handle.net/10203/74172-
dc.languageKorean-
dc.publisher대한전자공학회-
dc.titleGiga Bit급 저전력 Synchronous DRAM 구조에 대한 연구-
dc.title.alternativeA Study on the Low Power Architecture of Multi-giga bit Synchronous DRAM's-
dc.typeArticle-
dc.type.rimsART-
dc.citation.volume34C-
dc.citation.issue11-
dc.citation.beginningpage1-
dc.citation.endingpage11-
dc.citation.publicationname대한전자공학회 논문지-
dc.contributor.localauthor유회준-
dc.contributor.nonIdAuthor이장우-
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EE-Journal Papers(저널논문)
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