DC Field | Value | Language |
---|---|---|
dc.contributor.author | Park, G | ko |
dc.contributor.author | Han, S | ko |
dc.contributor.author | Hwang, T | ko |
dc.contributor.author | Shin, Hyung-Cheol | ko |
dc.date.accessioned | 2013-02-28T05:24:44Z | - |
dc.date.available | 2013-02-28T05:24:44Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 1999-12 | - |
dc.identifier.citation | JOURNAL OF THE KOREAN PHYSICAL SOCIETY, v.35, pp.S1003 - S1006 | - |
dc.identifier.issn | 0374-4884 | - |
dc.identifier.uri | http://hdl.handle.net/10203/72993 | - |
dc.description.abstract | We fabricated nano structure memory with SOI edge channel and a nano dot. The width of the edge channel was determined by the thickness of the recessed top-silicon layer of Silicon-On-Insulator (SOI) wafer and the size of the sidewall nano dot was determined by the Reactive Ion Etching (RIE) and E-Beam lithography. The memory has a threshold voltage shift of about 1 V for maximum programming voltage of 7 V and showed reasonable retention and endurance characteristics. | - |
dc.language | English | - |
dc.publisher | KOREAN PHYSICAL SOC | - |
dc.subject | ROOM-TEMPERATURE OPERATION | - |
dc.subject | SINGLE-ELECTRON MEMORY | - |
dc.subject | GATE | - |
dc.title | A nano-structure memory with SOI edge channel | - |
dc.type | Article | - |
dc.identifier.wosid | 000084389800064 | - |
dc.type.rims | ART | - |
dc.citation.volume | 35 | - |
dc.citation.beginningpage | S1003 | - |
dc.citation.endingpage | S1006 | - |
dc.citation.publicationname | JOURNAL OF THE KOREAN PHYSICAL SOCIETY | - |
dc.contributor.localauthor | Shin, Hyung-Cheol | - |
dc.contributor.nonIdAuthor | Park, G | - |
dc.contributor.nonIdAuthor | Han, S | - |
dc.contributor.nonIdAuthor | Hwang, T | - |
dc.type.journalArticle | Article; Proceedings Paper | - |
dc.subject.keywordPlus | ROOM-TEMPERATURE OPERATION | - |
dc.subject.keywordPlus | SINGLE-ELECTRON MEMORY | - |
dc.subject.keywordPlus | GATE | - |
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