DC Field | Value | Language |
---|---|---|
dc.contributor.author | Beomsup Kim | ko |
dc.date.accessioned | 2013-02-28T02:31:10Z | - |
dc.date.available | 2013-02-28T02:31:10Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 1997-07 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING, v.44, no.7, pp.577 - 586 | - |
dc.identifier.issn | 1057-7130 | - |
dc.identifier.uri | http://hdl.handle.net/10203/72301 | - |
dc.description.abstract | Since most digital phase-locked loops (DPLL's) used in digital data transmission receivers require both fast acquisition of input frequency and phase in the beginning and substantial jitter reduction in the steady state, the DPLL loop bandwidth is preferred to being adjusted accordingly, In this paper, three bandwidth adjusting (gear-shifting) algorithms are presented, which allow both fast acquisition and significant jitter reduction for each different noise environment and hardware requirement, These algorithms suggest an optimal sequence of control parameters for a dual-loop DPLL which achieves the fastest initial acquisition time by trying to minimize the jitter variance in any given time instant, The algorithms can be used for carrier recovery or clock recovery in mobile communications, local area networks and disk drives that require a short initial preamble period. | - |
dc.language | English | - |
dc.publisher | IEEE-Inst Electrical Electronics Engineers Inc | - |
dc.subject | RECOVERY | - |
dc.title | Dual-Loop DPLL Gear-Shifting Algorithm for Fast Synchronization | - |
dc.type | Article | - |
dc.identifier.wosid | A1997XK57300005 | - |
dc.identifier.scopusid | 2-s2.0-0031190631 | - |
dc.type.rims | ART | - |
dc.citation.volume | 44 | - |
dc.citation.issue | 7 | - |
dc.citation.beginningpage | 577 | - |
dc.citation.endingpage | 586 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING | - |
dc.contributor.localauthor | Beomsup Kim | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | bandwidth adjusting | - |
dc.subject.keywordAuthor | carrier recovery | - |
dc.subject.keywordAuthor | clock recovery | - |
dc.subject.keywordAuthor | digital phase-locked loop (DPLL) | - |
dc.subject.keywordAuthor | dual-loop DPLL | - |
dc.subject.keywordAuthor | fast acquisition | - |
dc.subject.keywordAuthor | fast locking | - |
dc.subject.keywordAuthor | gear-shifting | - |
dc.subject.keywordAuthor | locking speed | - |
dc.subject.keywordAuthor | short preamble | - |
dc.subject.keywordAuthor | time recovery | - |
dc.subject.keywordAuthor | zero phase shift | - |
dc.subject.keywordPlus | RECOVERY | - |
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