Register allocation - A hierarchical reduction approach

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dc.contributor.authorChaeryung Parkko
dc.contributor.authorKim, Taewhanko
dc.contributor.authorC.L. Liuko
dc.date.accessioned2013-02-28T01:58:28Z-
dc.date.available2013-02-28T01:58:28Z-
dc.date.created2012-02-06-
dc.date.created2012-02-06-
dc.date.issued1998-
dc.identifier.citationJOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY, v.19, no.3, pp.269 - 285-
dc.identifier.issn0922-5773-
dc.identifier.urihttp://hdl.handle.net/10203/72171-
dc.description.abstractA new approach to the problem of register allocation in high-level synthesis is presented. The algorithm employs a bottom-up transformational approach-sets of mutually exclusive variables in conditional branches are transformed into an "equivalent" set of nonmutually exclusive variables. The transformational approach is extended to the case of data-flow graphs with loops. A new register allocation algorithm is then used to produce an allocation for the nonmutually exclusive variables. From such an allocation, a corresponding allocation for the original set of mutually exclusive variables is derived. Our approach is particularly effective when there is a large number of nested conditional branches and loops in a data-flow graph.-
dc.languageEnglish-
dc.publisherKLUWER ACADEMIC PUBL-
dc.subjectDATA-PATH SYNTHESIS-
dc.subjectALGORITHM-
dc.titleRegister allocation - A hierarchical reduction approach-
dc.typeArticle-
dc.identifier.wosid000076279300005-
dc.identifier.scopusid2-s2.0-0032139424-
dc.type.rimsART-
dc.citation.volume19-
dc.citation.issue3-
dc.citation.beginningpage269-
dc.citation.endingpage285-
dc.citation.publicationnameJOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY-
dc.identifier.doi10.1023/A:1008073925779-
dc.contributor.localauthorKim, Taewhan-
dc.contributor.nonIdAuthorChaeryung Park-
dc.contributor.nonIdAuthorC.L. Liu-
dc.type.journalArticleArticle-
dc.subject.keywordPlusDATA-PATH SYNTHESIS-
dc.subject.keywordPlusALGORITHM-
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