Fabrication of a dual-gate-controlled Coulomb blockade transistor based on a silicon-on-insulator structure

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A new device structure for a single-electron-tunnelling transistor with a dual-gate geometry has been fabricated based on the silicon-on-insulator structure prepared by SIMOX wafers. The split gate of the transistor is the lower-level gate and located similar to 20 nm above the inversion layer 2DEG active channel, which yields strong carrier confinement with a fully controllable tunnelling potential barrier. The transistor operates at low temperatures and exhibits single-electron tunnelling behaviour through a nano-size quantum dot. The Coulomb blockade oscillation is demonstrated at 15 mK and its periodicity is 16.4 mV in the upper gate voltage. For the nonlinear transport regime, Coulomb staircases are clearly observed up to four current steps in the range of 100 mV drain-source bias. The I-V characteristics near zero bias display a typical Coulomb gap due to the one-electron charging effect. From the width of the blockade regime the dot capacitance is estimated to be similar to 13 aF.
Publisher
IOP PUBLISHING LTD
Issue Date
1998-12
Language
English
Article Type
Article
Keywords

SINGLE-ELECTRON TRANSISTOR; ROOM-TEMPERATURE; TRANSPORT

Citation

SEMICONDUCTOR SCIENCE AND TECHNOLOGY, v.13, no.12, pp.1463 - 1467

ISSN
0268-1242
DOI
10.1088/0268-1242/13/12/024
URI
http://hdl.handle.net/10203/71574
Appears in Collection
RIMS Journal Papers
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