Showing results 1 to 3 of 3
Low latency and power efficient VD using Register Exchanged state-mapping algorithm Seo S.-H.; Park, Sin Chong, Fifth International Workshop on System-on-Chip for Real-Time Applications, IWSOC 2005, v.2005, pp.380 - 384, 2005-07-20 |
Parallelized VLSI architecture of single stack based list sphere decoder Kim H.-S.; Seo S.-H.; Park, Sin Chong, 8th International Conference on Signal Processing, ICSP 2006, v.1, 2006-11-16 |
VLSI architecture of List Sphere Decoder Kim H.-S.; Seo S.-H.; Park, Sin Chong, 9th International Conference on Advanced Communication Technology, ICACT 2007, v.3, pp.1693 - 1696, 2007-02-12 |
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