Browse "College of Engineering(공과대학)" by Author Kyung, Chong-Min
Showing results 1 to 60 of 565
| 1.8mW, hybrid-pipelined H.264/AVC decoder for mobile devices Na, S.; Hwangbo, W.; Kim, J.; Lee, S.; Kyung, Chong-Min, 2007 IEEE Asian Solid-State Circuits Conference, A-SSCC, pp.192 - 195, 2007-11-12 |
| 2차원 그래픽스 연산을 위한 32비트 RISC 마이크로프로세서의 설계 = Design of a 32 bit RISC microprocessor for 2-D graphics operationslink 왕성문; Wang, Seong-Moon; et al, 한국과학기술원, 1991 |
| 32 비트 RISC 마이크로 프로세서 코어의 설계 = A design of 32-bit RISC microprocessor corelink 남상준; Nam, Sang-Joon; et al, 한국과학기술원, 1995 |
| 32bit RISC 마이크로 프로세서를 이용한 멀티미디어 시스템의 설계 및 구현 = Design and implementation of multimedia system using 32bit RISC microprocessorlink 양진혁; Yang, Jin-Hyuk; et al, 한국과학기술원, 1994 |
| 3D Geometry Graphics System Using Deferred Primitive Rendering with VLIW Geometry Processor Kyung, Chong-Min; Nam, S.J.; Kwon, Y.S.; Lee, J.H.; Im, Y.H., International Conference on Consumer Electronics(ICCE), 2000-06 |
| 3D Graphics System with VLIW Processor for Geometry Acceleration Kyung, Chong-Min; Jeon, Y.W.; Kwon, Y.S.; Im, Y.H.; Lee, J.H.; Nam, S.J.; Kim, B.W., IEEE Asia Pacific Conference on ASICs(AP-ASIC'2000), pp.367 - 370, 2000-08 |
| 3D-stacked L2 Cache Configuration for DVFS-enabled Processor to Minimize Overall Energy Consumption Kyung, Chong-Min, International Conference on Convergence and Hybrid Information Technology(ICHIT), International Conference on Convergence and Hybrid Information Technology(ICHIT), 2010 |
| 486호환 마이크로프로세서의 페이지 유닛과 캐쉬 유닛의 설계 = A design of paging unit and cache unit in 486-compatible microprocessorlink 김태훈; Kim, Tae-Hun; et al, 한국과학기술원, 1995 |
| A Floorplan-based Planning Methodology for Power and Clock Distribution in ASICs Kyung, Chong-Min; Yim, J.S., 36th Design Automation Conference(DAC), pp.766 - 771, 1999-06 |
| A clustering based linear ordering algorithm for netlist partitioning Seong, KS; Kyung, Chong-Min, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, v.E79A, no.12, pp.2185 - 2191, 1996-12 |
| A Compiled-code Simulator with Reduced Edge Evaluation Yang, W.S.; Park, In-Cheol; Kyung, Chong-Min, APCHDL'98, pp.107 - 110, 1998-07 |
| A Content-Aware Video Encoding Scheme Based on Single-Pass Consistent Quality Control Kim, Gi Won; Yi, Kang; Kyung, Chong-Min, IEEE TRANSACTIONS ON BROADCASTING, v.62, no.4, pp.800 - 816, 2016-12 |
| A cooperative surveillance system based on motion detection profile of car black-box = 차량용 블랙박스의 동작감지 프로파일을 기반으로 하는 협력 감시 시스템link Kim, Minseok; 김민석; et al, 한국과학기술원, 2016 |
| A DECORRELATION-BASED MONTE-CARLO SIMULATION - ITS APPLICATION TO YIELD STATISTICS OF CHARGE-REDISTRIBUTION A/D CONVERTERS LEE, YT; Kyung, Chong-Min; Kim, Choong Ki, PROCEEDINGS OF THE IEEE, v.74, no.5, pp.749 - 751, 1986-05 |
| A Double Structured Adaptive Finite Element Method for Semiconductor Device Analysis Kyung, Chong-Min; Choi, K.; Han, M.K.; Hahn, S.Y., The 3rd Biennial IEEE Conference on Electromagnetic Field Computation, 1988-12 |
| A Dynamic Search Range Algorithm for Stabilized Reduction of Memory Traffic in Video Encoder Jung, Jongpil; Kim, Jaemoon; Kyung, Chong-Min, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, v.20, pp.1041 - 1046, 2010-07 |
| A fast CABAC rate estimator for H.264/AVC mode decision Hahm, J.; Kim, J.; Kyung, Chong-Min, 2009 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2009, pp.929 - 932, IEEE Signal Processing Society, 2009-04-19 |
| A Fast Heuristic for Optimal CMOS Functional Cell Layout Generation Kyung, Chong-Min; Kwon, Y.J., International Symposium on Circuits and Systems, 1988-06 |
| A Fast Sine/Cosine Generator with Pipelined CORDIC and Table Lookup Method Shin, M.C.; Park, B.I.; Park, In-Cheol; Kyung, Chong-Min, '98 ASIC ON PROCEEDINGS, pp.281 - 284, 1998-10 |
| A Floorplanning Using Rectangular Voronoi Digranm and force-Directed Block shaping Kyung, Chong-Min; Choi, S.G., ICCAD-1991, 1991-04 |
| A Global router Using Simulated Annealing Applicable to Power and Ground Router Kyung, Chong-Min; Choi, S.G., Joint Technical Conference on Circuits/Systems, Computers and Communications, 1988-11 |
| A Graph Matching Algorithm for Circuit Partitioning and Placement in Rectilinear Region and Nonplanar Surface Park, In-Cheol; Kyung, Chong-Min, Joint Technical Conference on Circuits/Systems, Computers and Communications, pp.182 - 186, 대한전자공학회, 1988 |
| A Graphics Accelerator for Hidden Surface Removal and Color Shading S.O.Bae; K.I.Bang; Kyung, Chong-Min, JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, v.1, no.3, pp.239 - 255, 1991-09 |
| A Hardware Accelerator for Phong Illumination Model in 3-Dimentional Grahpics Kwon, Y.S.; Park, In-Cheol; Kyung, Chong-Min, HUMANTECH, pp.277 - 285, 1999 |
| A hardware accelerator for real time sliding window based pedestrian detection on high resolution images Khan, Asim; Khan, Muhammad Umar Karim; Bilal, Muhammad; Kyung, Chong-Min, 23rd IFIP/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2015, pp.46 - 66, Springer New York LLC, 2015-10 |
| A Hardware Accelerator for Scanline Interpolation and Hidden Surface Removal Kyung, Chong-Min; Eo, K.S.; Kim, S.S., International Conference on VLSI, 1989-08 |
| A Hardware Accelerator for the Specular Intensity of Phong Illumination Model in 3-Dimensional Kwon, Y. S.; Park, In-Cheol; Kyung, Chong-Min, ASP-DAC'2000, pp.559 - 564, 2000-01 |
| A HARDWARE ACCELERATOR FOR TWO-DIMENSIONAL IMAGE-ANALYSIS EO, KS; Kyung, Chong-Min, INTEGRATION-THE VLSI JOURNAL, v.6, no.3, pp.329 - 344, 1988-09 |
| A Heuristic Algorithm for Minimal Area CMOS Cell Layout Kyung, Chong-Min; Kwon, Y.J., Proceedings of 1987 Joint Technical Conference on Circuits and Systems, pp.111 - 116, 1987-07 |
| A Heuristic Algorithm for Minimal Area CMOS Cell Layout Y.J.Kwon; Kyung, Chong-Min, 전기학회논문지, v.24, no.6, pp.1060 - 1067, 1987-11 |
| A HEURISTIC STANDARD CELL PLACEMENT ALGORITHM USING CONSTRAINED MULTISTAGE GRAPH MODEL CHO, HG; Kyung, Chong-Min, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.7, no.11, pp.1205 - 1214, 1988-11 |
| A hierarchical circuit clustering algorithm with stable performance Kyoung, SJ; Seong, KS; Park, In-Cheol; Kyung, Chong-Min, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, v.E82A, no.9, pp.1987 - 1993, 1999-09 |
| A high-performance 2-D inverse transform architecture for the H.264/AVC decoder Hwangbo, W.; Kim, J.; Kyung, Chong-Min, 2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007, pp.1613 - 1616, 2007-05-27 |
| A Hybrid Shadow testing Scheme During Ray Tracing Kyung, Chong-Min; Eo, K.S.; Choi, H.K., Joint Technical Conference on Circuits/Systems, Computers and Communications, 1988-11 |
| A Hybrid Shadow Testing Scheme during Ray Tracing Eo, Kil Su; Kyung, Chong-Min, International Computer Symposium, ICS 88, 1988-12 |
| A lossless embedded compression algorithm for high definition video coding Kim, J.; Kim, J.; Kyung, Chong-Min, 2009 IEEE International Conference on Multimedia and Expo, ICME 2009, pp.193 - 196, 123, 2009-06-28 |
| A Lossless Embedded Compression Using Significant Bit Truncation for HD Video Coding Kim, Jaemoon; Kyung, Chong-Min, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, v.20, pp.848 - 860, 2010-06 |
| A low cost single-pass fractional motion estimation architecture using bit clipping for H.264 video codec Kim, G.; Kim, J.; Kyung, Chong-Min, 2010 IEEE International Conference on Multimedia and Expo, ICME 2010, pp.661 - 666, IEEE, 2010-07-19 |
| A low error add and shift-based efficient implementation of base-2 logarithm Kareem, Pervaiz; Naqvi, Syed Rameez; Kyung, Chong-Min, 2017 International Conference on Electrical Engineering, ICEE 2017, Institute of Electrical and Electronics Engineers Inc., 2017-11-13 |
| A Low-Complexity Pedestrian Detection Framework for Smart Video Surveillance Systems Bilal, Muhammad; Khan, Asim; Khan, Muhammad Umar Karim; Kyung, Chong-Min, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY, v.27, no.10, pp.2260 - 2273, 2017-10 |
| A low-energy video event data recorder using dual image/video codec Jung, Jongpil; Kyung, Chong-Min; Lim, Jinyeon; Lee, Seung Han; Lee, Jungeon; Yang, Jin young, 11th IEEE International Conference on Advanced Video and Signal Based Surveillance(AVSS2014), pp.277 - 282, IEEE Signal Processing Society and IEEE Computer Society, 2014-08-29 |
| A low-power deblocking filter architecture for H.264 advanced video coding Kim, J.; Na, S.; Kyung, Chong-Min, 2007 IFIP International Conference on Very Large Scale Integration, VLSI-SoC, pp.190 - 193, 123, 2007-10-15 |
| A Memory- and Accuracy-Aware Gaussian Parameter-Based Stereo Matching Using Confidence Measure Lee, Yeongmin; Kyung, Chong-Min, IEEE TRANSACTIONS ON PATTERN ANALYSIS AND MACHINE INTELLIGENCE, v.43, no.6, pp.1845 - 1858, 2021-06 |
| A multi-layer motion estimation scheme for spatial scalability in H.264/AVC scalable extension Na, S.; Kyung, Chong-Min, 2009 IEEE International Conference on Multimedia and Expo, ICME 2009, pp.69 - 72, 123, 2009-06-28 |
| A Multi-Threading MPEG Processor with Variable Issue Modes Yang, W.S.; Kim, H.S.; Park, In-Cheol; Shin, M.C.; Kyung, Chong-Min, International Conference on VLSI and CAD(ICVC'99), pp.545 - 548, 1999-10 |
| A Multitransform Architecture for H.264/AVC High-Profile Coders Hwangbo, Woong; Kyung, Chong-Min, IEEE TRANSACTIONS ON MULTIMEDIA, v.12, pp.157 - 167, 2010-04 |
| A New Design Rule Checker Based on Corner Checking and Bit Mapping Kyung, Chong-Min; Eo, K.S., International Symposium on Circuits and Systems, pp.1289 - 1292, 1985-06 |
| A New Floorplanning Algorithm Using Force-Directed Block Shaping Kyung, Chong-Min; Choi, S.G., JTC-CSCC91, 1991-07 |
| A New Layout Scheme for Macro Cells Kyung, Chong-Min; Lee, P.H., International Conference on VLSI and CAD, 1991-10 |
| A New Parallel Hardware Architecture for Fast Polygon Rendering Kyung, Chong-Min; Bae, S.O.; Song, G.S., Joint Technical Conference on Circuits/Systems, Computers and Communications, 1990-12 |
| A new parallel ray-tracing system based on object decomposition Kim, HJ; Kyung, Chong-Min, VISUAL COMPUTER, v.12, no.5, pp.244 - 253, 1996 |
| A New Pin Assignment Algorithm for Building Block Layout Kyung, Chong-Min; Choi, S.G., JTC-CSCC, 1992-07 |
| A new RTL debugging methodology in FPGA-based verification platform Yang, S.; Shim, H.; Yang, W.; Kyung, Chong-Min, Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits, pp.180 - 183, 2004-08-04 |
| A new single-clock flip-flop for half-swing clocking Kwon, YS; Park, In-Cheol; Kyung, Chong-Min, IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, v.E82A, no.11, pp.2521 - 2526, 1999-11 |
| A New Single-Clock Flip-Flop for Half-Swing Clocking Kwon, Y.S.; Park, B.I.; Park, In-Cheol; Kyung, Chong-Min, ASP-DAC'99, pp.117 - 120, ASP-DAC, 1999-01 |
| A New State Encoding Algorithm by the Construction of Hypercube Kyung, Chong-Min; Park, S.S., International Conference on VLSI and CAD, 1993-11 |
| A Novel Bus Interface and Motion Compensation Architecture for H.264/AVC with Reduced Memory Access Kyung, Chong-Min; Kim, Jaemoon; Hwangbo, Woong, 제16회 한국반도체학술대회(KCS), 2009 |
| A P-Channel Schottky-Clamped MOSFET Utilizing Boron-Doped Sidewall Oxide Kim, Choong Ki; Kyung, Chong-Min; Oh, C.S., International Symposium on VLSI Technology,Systems and Applications, pp.250 - 253, 1985-05 |
| A PRACTICAL DESIGN METHOD FOR INSTRUCTION DECODER PLAS FOR MICROPROGRAMMED CONTROLLERS KIM, HH; Hwang, Seung-Ho; Kyung, Chong-Min, MICROPROCESSORS AND MICROSYSTEMS, v.17, no.8, pp.481 - 488, 1993-10 |
| A prediction packetizing scheme for reducing channel traffic in transaction-level hardware/software co-emulation Lee, J.-G.; Chung, M.-K.; Ahn, K.-Y.; Lee, S.-H.; Kyung, Chong-Min, Design, Automation and Test in Europe, DATE '05, pp.384 - 389, DATE '05, 2005-03-07 |
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- 23,134 2020 - 2024
- 75,382 2010 - 2019
- 57,250 2000 - 2009
- 30,842 1990 - 1999
- 9,025 1980 - 1989