Showing results 3 to 6 of 6
Power-aware Partitioned Cache Architectures Kim, Soontae; Kandemir, M.; Sivasubramaniam, A.; Irwin, M.J.; Geethanjali, E., ACM/IEEE International Symposium on Low Power Electronics and Design, pp.64 - 67, 2001-08 |
Predictive Precharging for Bitline Leakage Energy Reduction Kim, Soontae; Vijaykrishnan, N.; Kandemir, M.; Irwin, M.J., 15th Annual IEEE International ASIC/SOC Conference, 2002. , pp.36 - 40, 2002-09 |
Scheduling Reusable Instructions for Power Reduction Hu, J.S.; Vijaykrishnan, N.; Kim, Soontae; Kandemir, M.; Irwin, M.J., Proceedings Design, Automation and Test in Europe Conference and Exhibition, 2004. , v.1, pp.148 - 153, 2004-02 |
Use of local memory for efficient Java execution Tomar, S.; Kim, Soontae; Vijaykrishnan, N.; Kandemir, M.; Irwin, M.J., IEEE International Conference on Computer Design, pp.468 - 473, 2001-09 |
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