Showing results 7 to 10 of 10
I/O power estimation and analysis of high-speed channels in Through-Silicon Via (TSV)-based 3D IC Kim, Joungho; Cho, J.; Pak, J.S.; Song, T.; Kim, J.; Lee, H.; Lee, J.; et al, 2010 IEEE 19th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2010, pp.41 - 44, IEEE, 2010-10-25 |
Modeling and analysis of coupling between TSVs, metal, and RDL interconnects in TSV-based 3D IC with silicon interposer Yoon, K.; Kim, G.; Lee, W.; Song, T.; Lee, J.; Lee, H.; Park, K.; et al, 2009 11th Electronic Packaging Technology Conference, EPTC 2009, pp.702 - 706, 2009-12-09 |
Modeling and analysis of die-to-die vertical coupling in 3-D IC Lee, S.; Kim, G.; Kim, J.; Song, T.; Lee, J.; Lee, H.; Park, K.; et al, 2009 11th Electronic Packaging Technology Conference, EPTC 2009, pp.707 - 711, 2009-12-09 |
Through Silicon Via (TSV) shielding structures Cho, J.; Kim, Joungho; Song, T.; Pak, J.S.; Kim, J.; Lee, H.; Lee, J.; et al, 2010 IEEE 19th Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2010, pp.269 - 272, IEEE, 2010-10-25 |
Discover