Browse "College of Engineering(공과대학)" by Type Conference
Showing results 1241 to 1260 of 91091
| A 2.7 to 9.3 GHz CMOS wideband amplifier combined with high pass filter for UWB system Jung, M.-S.; Kim, C.-W.; Anh, P.T.; Kim, H.-T.; Lee, Sang-Gug, 7th International Conference on Advanced Communication Technology, ICACT 2005, v.1, no.0, pp.57 - 60, 7th International Conference on Advanced Communication Technology, 2005-02-21 |
| A 2.71nJ/Pixel 3D-Stacked Gaze-Activated Object-Recognition System for Low-Power Mobile HMD Applications Yoo, Hoi-Jun; Hong, In-Joon; Bong, Kyeongryeol; Shin, Dongjoo; Park, Seongwook; Lee, Kyuho; Kim, Youchang, IEEE International Solid- State Circuits Conference, pp.326 - 327, IEEE, 2015-02-25 |
| A 2.79-mW 0.5%-THD CMOS Current Driver IC for Portable Electrical Impedance Tomography System Jang, Jaeeun; Kim, Minseo; Bae, Joonsung; Yoo, Hoi-Jun, IEEE Asian Solid-State Circuits Conference 2017, IEEE Asian Solid-State Circuits Conference 2017, 2017-11 |
| A 2.85mW 0.12mm2 1.0V 11-bit 20-MS/s algorithmic ADC in 65nm CMOS Nam, J.-W.; Jeon, Y.-D.; Cho, Y.-K.; Lee, Sang-Gug; Kwon, J.-K., 35th European Solid-State Circuits Conference, ESSCIRC 2009, pp.468 - 471, 2009-09-14 |
| A 20 Gbps 1-Tap Decision Feedback Equalizer with Unfixed Tap Coefficient Kim, Yong-Hun; Kim, Lee-Sup, 2012 IEEE International Symposium on Circuits and Systems, IEEE, 2012-05-21 |
| A 20 μw contact impedance sensor for wireless body-area-network transceiver Song, Kiseok; Bae, Joonsung; Yan, Long; Yoo, Hoi-Jun, IEEE Custom Integrated Circuits Conference - CICC 2011, IEEE, 2011-09-19 |
| A 20-MHz 2.3-mW Receiver and a 25-V Transmitter for Ultrasound Capsule Endoscopy Jeong, Kyeongwon; Choi, Jaesuk; Yun, Gichan; Choi, Injun; Son, Jeehoon; Hwang, Jae Youn; Ha, Sohmyung; et al, 2022 IEEE Asian Solid-State Circuits Conference, A-SSCC 2022, Institute of Electrical and Electronics Engineers Inc., 2022-11 |
| A 200mA digital low-drop-out regulator with coarse-fine dual loop in mobile application processors Lee, Yong-Jin; Jung, Min-Yong; Shashank Singh; Kong, Tae-Hwang; Kim. Dae-Yong; Kim, Kwang-Ho; Kim, Sang-Ho; et al, 2016 IEEE International Solid-State Circuits Conference, ISSCC 2016, pp.150 - U201, IEEE, 2016-02-02 |
| A 200Mbps 0.02nJ/b dual-mode inductive coupling transceiver for cm-range interconnection Lee, S.; Yoo, J.; Yoo, Hoi-Jun, 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008, pp.1954 - 1957, IEEE, 2008-05-18 |
| A 200MHz/90dB Gain Range CMOS VGA Cho, Gyu-Hyeong, pp.1 - 4, IEEE, 2000 |
| A 201.4GOPS 496mW real-time multi-object recognition processor with bio-inspired neural perception engine Kim, Joo-Young; Kim, Minsu; Lee, Seungjin; Oh, Jinwook; Kim, Kwanho; Oh, Sejong; Woo, Jeong-Ho; et al, 2009 IEEE International Solid-State Circuits Conference ISSCC 2009, Institute of Electrical and Electronics Engineers Inc., 2009-02-08 |
| A 2048-Point FFT Processor Based on Twiddle Factor Table Reduction Kim , JH; Park, In-Cheol, IEEE Symposium on Low-Power and High-Speed Chips (COOL Chips 2007), pp.351 - 364, IEEE, 2007-04 |
| A 20Gb/s 1:4 DEMUX without inductors in 0.13um CMOS Kim, B.-G.; Kim, Lee-Sup; Byun, S.; Yu, H.-K., 2006 IEEE International Solid-State Circuits Conference, ISSCC, ISSCC, 2006-02-06 |
| A 20Gb/s Transceiver with Framed-Pulsewidth Modulation in 40nm CMOS Jeon, Sejun; Kwon, WooHyun; Yoon, Taehun; Yoon, Jong-Hyeok; Kwon, Kyeongha; Yang, Jaehyeok; Bae, Hyeon-Min, 65th International Solid-State Circuits Conference (ISSCC), pp.270, IEEE, 2018-02-11 |
| A 210 nW 29.3 ppm/C 0.7 V Voltage Reference with a Temperature Range of -50 to 130 C in 0.13 um CMOS Lee, Junghyup; Cho, SeongHwan, IEEE Symposium on VLSI Circuits, pp.278 - 279, IEEE, 2011-06-17 |
| A 210MHz 15mW unified vector and transcendental function unit for handheld 3-D graphics systems Nam, B.-G.; Kim, H.; Yoo, Hoi-Jun, 2006 IEEE Asian Solid-State Circuits Conference, ASSCC 2006, pp.95 - 98, 2006-11-13 |
| A 210mW graphics LSI implementing full 3D pipeline with 264Mtexels/s texturing for mobile multimedia applications Woo, R.; Cho,i S.; Sohn, J.-H.; Song, S.-J.; Bae, Y.-D.; Yoon, C.-W.; Nam, B.-G.; et al, 2003 Digest of Technical Papers, 2003-02-09 |
| A 211 GOPS/W dual-mode real-time object recognition processor with Network-on-Chip Kim, Kwanho; Kim, Joo-Young; Lee, Seungjin; Kim, Minsu; Yoo, Hoi-Jun, 34th European Solid-State Circuits Conference, ESSCIRC 2008, pp.462 - 465, IEEE, 2008-09-15 |
| A 2144.2-bits/min/mW 5-Heterogeneous PE-based Domain-Specific Reconfigurable Array Processor for 8-Ch Wearable Brain-Computer Interface SoC Byun, Wooseok; Je, Minkyu; Kim, Ji-Hoon, 35th Symposium on VLSI Circuits, VLSI Circuits 2021, Institute of Electrical and Electronics Engineers Inc., 2021-06 |
| A 21fJ/conv-step 9 ENOB 1.6GS/s 2x Time-Interleaved FATI SAR ADC with Background Offset and Timing-Skew Calibration in 45nm CMOS Sung, BRS; Jo, DS; Jang, IH; Lee, DS; You, YS; Lee, YH; Park, HJ; et al, International Solid-State Circuits Conference (ISSCC), IEEE, 2015-02-25 |
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