Control signal layout ordering scheme minimising cross-coupling effect in deep-submicrometre datapath design

Abstract

In deep submicrometre technology, an inter-wire coupling capacitance dominates wire loading and makes interconnect delays very data-dependent. Reducing this cross-coupling effect is crucial for high-speed lower-power operation. A layout scheme is proposed for datapath control signals which reduces the switching Fewer by 10% and wire delays by 15% for 0.25 mu m microprocessor examples.