DC Field | Value | Language |
---|---|---|
dc.contributor.author | LEE, SH | ko |
dc.contributor.author | PARK, SB | ko |
dc.contributor.author | Park, Kyu Ho | ko |
dc.date.accessioned | 2013-02-27T13:13:42Z | - |
dc.date.available | 2013-02-27T13:13:42Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 1995-01 | - |
dc.identifier.citation | IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, v.E78A, no.1, pp.142 - 145 | - |
dc.identifier.issn | 0916-8508 | - |
dc.identifier.uri | http://hdl.handle.net/10203/68778 | - |
dc.description.abstract | A simple method is presented to calculate the parasitic capacitance effect in the propagation delay of series-connected MOS (SCM) structures. This method divides SCM circuits into two parts and accurately calculates the contribution of each part to the difference from the delay without parasitic capacitances. | - |
dc.language | English | - |
dc.publisher | IEICE-INST ELECTRON INFO COMMUN ENG | - |
dc.title | THE EFFECT OF INTERNAL PARASITIC CAPACITANCES IN SERIES-CONNECTED MOS STRUCTURE | - |
dc.type | Article | - |
dc.identifier.wosid | A1995QD76200022 | - |
dc.identifier.scopusid | 2-s2.0-0029208124 | - |
dc.type.rims | ART | - |
dc.citation.volume | E78A | - |
dc.citation.issue | 1 | - |
dc.citation.beginningpage | 142 | - |
dc.citation.endingpage | 145 | - |
dc.citation.publicationname | IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES | - |
dc.contributor.localauthor | Park, Kyu Ho | - |
dc.contributor.nonIdAuthor | LEE, SH | - |
dc.contributor.nonIdAuthor | PARK, SB | - |
dc.type.journalArticle | Letter | - |
dc.subject.keywordAuthor | COMPUTER AIDED DESIGN (CAD) | - |
dc.subject.keywordAuthor | MODELING AND SIMULATION, PARASITIC CAPACITANCE | - |
dc.subject.keywordAuthor | DELAY MODEL | - |
dc.subject.keywordAuthor | SERIES-CONNECTED MOS STRUCTURE | - |
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