Optimal Bit-level Arithmetic Optimization for High-Speed Circuits

Abstract

In terms of speed, the Wallace-tree compressor (i.e. bit-level carry-save addition array) is widely recognised as one of the most effective schemes for implementing arithmetic computations in VLSI design. However, the scheme has been applied only in a rather restrictive way, i.e. for implementing fast multipliers and for generating fixed structures without considering the characteristic of the input signals. The authors address the problem of optimising arithmetic circuits to overcome those limitations. A polynomial time algorithm is presented which generates a delay-optimal carry-save addition structure of an arithmetic circuit with uneven signal arrival profiles. This algorithm has been applied to the optimisation of high-speed digital filters and 5-30% savings have been achieved in the overall filter implementation in comparison to the standard carry-save implementation.