DC Field | Value | Language |
---|---|---|
dc.contributor.author | kyuhyun lim | ko |
dc.contributor.author | chan-hong park | ko |
dc.contributor.author | dal-soo kim | ko |
dc.contributor.author | Kim, Beom-Sup | ko |
dc.date.accessioned | 2013-02-27T09:31:28Z | - |
dc.date.available | 2013-02-27T09:31:28Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2000-06 | - |
dc.identifier.citation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.35, no.6, pp.807 - 815 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | http://hdl.handle.net/10203/67760 | - |
dc.description.abstract | This paper describes a low-noise phase-locked loop (PLL) design method to achieve minimum jitter from a given PLL circuit topology. An optimal loop-bandwidth design method, derived from a discrete-time PLL model, further improves the jitter characteristics of a PLL already somewhat enhanced by optimizing individual circuit components. The described method not only estimates the timing jitter of a PLL, but also finds the optimal bandwidth minimizing the overall PLL jitter, a prototype PLL fabricated in a 0.6-mu m CMOS technology is tested. The measurement shows significant performance improvement by using the proposed method. The measured rms and peak-to-peak jitter of the PLL at the optimal loop-bandwidth are 3.1 and 22 ps, respectively. | - |
dc.language | English | - |
dc.publisher | IEEE-Inst Electrical Electronics Engineers Inc | - |
dc.subject | OSCILLATORS | - |
dc.title | A Low-Noise Phase-Locked Loop Design by Loop Bandwidth Optimization | - |
dc.type | Article | - |
dc.identifier.wosid | 000087549400002 | - |
dc.identifier.scopusid | 2-s2.0-0033689116 | - |
dc.type.rims | ART | - |
dc.citation.volume | 35 | - |
dc.citation.issue | 6 | - |
dc.citation.beginningpage | 807 | - |
dc.citation.endingpage | 815 | - |
dc.citation.publicationname | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.contributor.localauthor | Kim, Beom-Sup | - |
dc.contributor.nonIdAuthor | kyuhyun lim | - |
dc.contributor.nonIdAuthor | chan-hong park | - |
dc.contributor.nonIdAuthor | dal-soo kim | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | clock generator | - |
dc.subject.keywordAuthor | clock synthesis | - |
dc.subject.keywordAuthor | discrete-time domain analysis | - |
dc.subject.keywordAuthor | low-noise phase-locked loop | - |
dc.subject.keywordAuthor | optimal loop bandwidth | - |
dc.subject.keywordAuthor | timing jitter | - |
dc.subject.keywordPlus | OSCILLATORS | - |
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