Power-efficient gate control of synchronous boost converters with high output voltage
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Woo, YJ | ko |
| dc.contributor.author | Cho, Gyu-Hyeong | ko |
| dc.date.accessioned | 2008-08-01T01:08:17Z | - |
| dc.date.available | 2008-08-01T01:08:17Z | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.issued | 2007-02 | - |
| dc.identifier.citation | ELECTRONICS LETTERS, v.43, pp.156 - 157 | - |
| dc.identifier.issn | 0013-5194 | - |
| dc.identifier.uri | http://hdl.handle.net/10203/6754 | - |
| dc.description.abstract | A half output voltage swing gate driving scheme is presented for high voltage single chip DC/DC converters. In the proposed scheme the energy for the PMOS gate drive is reused for the NMOS gate drive, and switching loss is reduced. A high speed and area-efficient high voltage level shifter is also realised. A prototype is implemented using a 0.5 mu m 40 V power BiCMOS process. | - |
| dc.language | English | - |
| dc.language.iso | en_US | en |
| dc.publisher | INST ENGINEERING TECHNOLOGY-IET | - |
| dc.title | Power-efficient gate control of synchronous boost converters with high output voltage | - |
| dc.type | Article | - |
| dc.identifier.wosid | 000248317400014 | - |
| dc.identifier.scopusid | 2-s2.0-34248362413 | - |
| dc.type.rims | ART | - |
| dc.citation.volume | 43 | - |
| dc.citation.beginningpage | 156 | - |
| dc.citation.endingpage | 157 | - |
| dc.citation.publicationname | ELECTRONICS LETTERS | - |
| dc.identifier.doi | 10.1049/el:20072929 | - |
| dc.embargo.liftdate | 9999-12-31 | - |
| dc.embargo.terms | 9999-12-31 | - |
| dc.contributor.localauthor | Cho, Gyu-Hyeong | - |
| dc.contributor.nonIdAuthor | Woo, YJ | - |
| dc.type.journalArticle | Article | - |
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