DC Field | Value | Language |
---|---|---|
dc.contributor.author | Kim, JS | ko |
dc.contributor.author | Choi, YS | ko |
dc.contributor.author | Yoo, Hoi-Jun | ko |
dc.contributor.author | Seo, KS | ko |
dc.date.accessioned | 2008-07-23T06:11:10Z | - |
dc.date.available | 2008-07-23T06:11:10Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 1998-07 | - |
dc.identifier.citation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.33, no.7, pp.1096 - 1102 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | http://hdl.handle.net/10203/6357 | - |
dc.description.abstract | The 6F(2) cell is widely known for its small area, but its sensing is unstable due to the large array noises. A new low-noise sensing scheme for a 6F(2) DRAM cell is proposed, employing two noise reduction methods: the divided sense and combined restore scheme and the bit-line noise absorbing scheme. They can reduce word-line to bit-line as well as bit-line to bit-line coupling noises, The bit-line noise is reduced to 85% of that of a conventional scheme,vith only 0.05% area overhead, which is negligible compared to the area saving by using a 6F(2) cell. The total chip area and the sensing time can be reduced to 85 and 87%, respectively, compared to conventional DRAM, A 2 kbit DRAM test chip with a 6F(2) cell is fabricated using 256 M DRAM technology, and its stable operations are confirmed. | - |
dc.language | English | - |
dc.language.iso | en_US | en |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | A low-noise folded bit-line sensing architecture for multigigabit DRAM with ultrahigh-density 6F(2) cell | - |
dc.type | Article | - |
dc.identifier.wosid | 000074397700019 | - |
dc.identifier.scopusid | 2-s2.0-0032123025 | - |
dc.type.rims | ART | - |
dc.citation.volume | 33 | - |
dc.citation.issue | 7 | - |
dc.citation.beginningpage | 1096 | - |
dc.citation.endingpage | 1102 | - |
dc.citation.publicationname | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.embargo.liftdate | 9999-12-31 | - |
dc.embargo.terms | 9999-12-31 | - |
dc.contributor.localauthor | Yoo, Hoi-Jun | - |
dc.contributor.nonIdAuthor | Kim, JS | - |
dc.contributor.nonIdAuthor | Choi, YS | - |
dc.contributor.nonIdAuthor | Seo, KS | - |
dc.type.journalArticle | Article; Proceedings Paper | - |
dc.subject.keywordAuthor | amplifier noise | - |
dc.subject.keywordAuthor | DRAM chips | - |
dc.subject.keywordAuthor | integrated circuit design | - |
dc.subject.keywordAuthor | memory architecture | - |
dc.subject.keywordAuthor | semiconductor memories | - |
dc.subject.keywordAuthor | very large scale integration | - |
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