Dual Vt Self-timed CMOS Logic for Low Subthreshold Current Multi-Gigabit Synchronous DRAM
| DC Field | Value | Language |
|---|---|---|
| dc.contributor.author | Yoo, Hoi-Jun | ko |
| dc.date.accessioned | 2008-07-23T06:06:27Z | - |
| dc.date.available | 2008-07-23T06:06:27Z | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.created | 2012-02-06 | - |
| dc.date.issued | 1998-09 | - |
| dc.identifier.citation | IEEE TANS. CIRCUITS SYST. II, v.0, no.0, pp.0 - 0 | - |
| dc.identifier.issn | 1057-7130 | - |
| dc.identifier.uri | http://hdl.handle.net/10203/6355 | - |
| dc.language | English | - |
| dc.language.iso | en_US | en |
| dc.publisher | Institute of Electrical and Electronics Engineers | - |
| dc.title | Dual Vt Self-timed CMOS Logic for Low Subthreshold Current Multi-Gigabit Synchronous DRAM | - |
| dc.type | Article | - |
| dc.type.rims | ART | - |
| dc.citation.volume | 0 | - |
| dc.citation.issue | 0 | - |
| dc.citation.beginningpage | 0 | - |
| dc.citation.endingpage | 0 | - |
| dc.citation.publicationname | IEEE TANS. CIRCUITS SYST. II | - |
| dc.embargo.liftdate | 9999-12-31 | - |
| dc.embargo.terms | 9999-12-31 | - |
| dc.contributor.localauthor | Yoo, Hoi-Jun | - |
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