Dual Vt Self-timed CMOS Logic for Low Subthreshold Current Multi-Gigabit Synchronous DRAM

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dc.contributor.authorYoo, Hoi-Junko
dc.date.accessioned2008-07-23T06:06:27Z-
dc.date.available2008-07-23T06:06:27Z-
dc.date.created2012-02-06-
dc.date.created2012-02-06-
dc.date.issued1998-09-
dc.identifier.citationIEEE TANS. CIRCUITS SYST. II, v.0, no.0, pp.0 - 0-
dc.identifier.issn1057-7130-
dc.identifier.urihttp://hdl.handle.net/10203/6355-
dc.languageEnglish-
dc.language.isoen_USen
dc.publisherInstitute of Electrical and Electronics Engineers-
dc.titleDual Vt Self-timed CMOS Logic for Low Subthreshold Current Multi-Gigabit Synchronous DRAM-
dc.typeArticle-
dc.type.rimsART-
dc.citation.volume0-
dc.citation.issue0-
dc.citation.beginningpage0-
dc.citation.endingpage0-
dc.citation.publicationnameIEEE TANS. CIRCUITS SYST. II-
dc.embargo.liftdate9999-12-31-
dc.embargo.terms9999-12-31-
dc.contributor.localauthorYoo, Hoi-Jun-
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