DC Field | Value | Language |
---|---|---|
dc.contributor.author | Lee, Kang-Min | ko |
dc.contributor.author | Lee, Se-Joong | ko |
dc.contributor.author | Yoo, Hoi-Jun | ko |
dc.date.accessioned | 2008-07-22T09:00:50Z | - |
dc.date.available | 2008-07-22T09:00:50Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2006-02 | - |
dc.identifier.citation | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.14, pp.148 - 160 | - |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.uri | http://hdl.handle.net/10203/6296 | - |
dc.description.abstract | An energy-efficient network-on-chip (NoC) is presented for possible application to high-performance system-on-hip (SoC) design. It incorporates heterogeneous intellectual properties (IPs) such as multiple RISCs and SRAMs, a reconfigurable logic array, an off-chip gateway, and a 1.6-GHz phase-locked loop (PLL). Its hierarchically-star-connected on-chip network provides the integrated IN, which operate at different clock frequencies, with packet-switched serial-communication infrastructure. Various low-power techniques such as low-swing signaling, partially activated crossbar, serial link coding, and clock frequency scaling are devised, and applied to achieve the power-efficient on-chip communications. The 5 x 5 mm(2) chip containing all the above features is fabricated by 0.18-mu m CMOS process and successfully measured and demonstrated on a system evaluation board where multimedia applications run. The fabricated chip can deliver 11.2-GB/s aggregated bandwidth at 1.6-GHz signaling frequency. The chip consumes 160 mW and the on-chip network dissipates less than 51 mW. | - |
dc.language | English | - |
dc.language.iso | en_US | en |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Low-power network-on-chip for high-performance SoC design | - |
dc.type | Article | - |
dc.identifier.wosid | 000236131600005 | - |
dc.identifier.scopusid | 2-s2.0-33645011974 | - |
dc.type.rims | ART | - |
dc.citation.volume | 14 | - |
dc.citation.beginningpage | 148 | - |
dc.citation.endingpage | 160 | - |
dc.citation.publicationname | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.identifier.doi | 10.1109/TVLSI.2005.863753 | - |
dc.embargo.liftdate | 9999-12-31 | - |
dc.embargo.terms | 9999-12-31 | - |
dc.contributor.localauthor | Yoo, Hoi-Jun | - |
dc.contributor.nonIdAuthor | Lee, Kang-Min | - |
dc.contributor.nonIdAuthor | Lee, Se-Joong | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | bus coding | - |
dc.subject.keywordAuthor | crossbar | - |
dc.subject.keywordAuthor | interconnection | - |
dc.subject.keywordAuthor | low-power | - |
dc.subject.keywordAuthor | network-on-chip (NoC) | - |
dc.subject.keywordAuthor | on-chip network | - |
dc.subject.keywordAuthor | packet | - |
dc.subject.keywordAuthor | serial communications | - |
dc.subject.keywordAuthor | small swing | - |
dc.subject.keywordAuthor | system-on-chip (SoC) | - |
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