A 7.1-GB/s low-power rendering engine in 2-D array-embedded memory logic CMOS for portable multimedia system

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dc.contributor.authorPark, YHko
dc.contributor.authorHan, SHko
dc.contributor.authorLee, JHko
dc.contributor.authorYoo, Hoi-Junko
dc.date.accessioned2008-07-22T08:28:16Z-
dc.date.available2008-07-22T08:28:16Z-
dc.date.created2012-02-06-
dc.date.created2012-02-06-
dc.date.issued2001-06-
dc.identifier.citationIEEE JOURNAL OF SOLID-STATE CIRCUITS, v.36, no.6, pp.944 - 955-
dc.identifier.issn0018-9200-
dc.identifier.urihttp://hdl.handle.net/10203/6282-
dc.description.abstractA single-chip rendering engine that consists of a DRAM frame buffer, a SRAM serial access memory, pixel/edge processor array and 32-b RISC core is proposed for low-power three-dimensional (3-D) graphics in portable systems. The main features are two-dimensional (2-D) hierarchical octet tree (HOT) array structure with bandwidth amplification, three dedicated network schemes, virtual page mapping, memory-coupled logic pipeline, low-power operation, 7.1-GB/s memory bandwidth, and 11.1-Mpolygon/s drawing speed, The 56-mm(2) prototype die integrating one edge processor, eight pixel processors, eight frame buffers, and a RISC core are fabricated using 0.35-mum CMOS embedded memory logic (EML) technology with four poly lavers and three metal layers, The fabricated test chip, 590 mW at 100-MHz 3.3-V operation, is demonstrated with a host PC through a PCI bridge.-
dc.languageEnglish-
dc.language.isoen_USen
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.titleA 7.1-GB/s low-power rendering engine in 2-D array-embedded memory logic CMOS for portable multimedia system-
dc.typeArticle-
dc.identifier.wosid000168887000009-
dc.identifier.scopusid2-s2.0-0035368865-
dc.type.rimsART-
dc.citation.volume36-
dc.citation.issue6-
dc.citation.beginningpage944-
dc.citation.endingpage955-
dc.citation.publicationnameIEEE JOURNAL OF SOLID-STATE CIRCUITS-
dc.embargo.liftdate9999-12-31-
dc.embargo.terms9999-12-31-
dc.contributor.localauthorYoo, Hoi-Jun-
dc.contributor.nonIdAuthorPark, YH-
dc.contributor.nonIdAuthorHan, SH-
dc.contributor.nonIdAuthorLee, JH-
dc.type.journalArticleArticle-
dc.subject.keywordAuthorembedded memory-
dc.subject.keywordAuthorembedded logic-
dc.subject.keywordAuthor3-D graphic rendering-
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