DC Field | Value | Language |
---|---|---|
dc.contributor.author | Park, YH | ko |
dc.contributor.author | Han, SH | ko |
dc.contributor.author | Lee, JH | ko |
dc.contributor.author | Yoo, Hoi-Jun | ko |
dc.date.accessioned | 2008-07-22T08:28:16Z | - |
dc.date.available | 2008-07-22T08:28:16Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2001-06 | - |
dc.identifier.citation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.36, no.6, pp.944 - 955 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | http://hdl.handle.net/10203/6282 | - |
dc.description.abstract | A single-chip rendering engine that consists of a DRAM frame buffer, a SRAM serial access memory, pixel/edge processor array and 32-b RISC core is proposed for low-power three-dimensional (3-D) graphics in portable systems. The main features are two-dimensional (2-D) hierarchical octet tree (HOT) array structure with bandwidth amplification, three dedicated network schemes, virtual page mapping, memory-coupled logic pipeline, low-power operation, 7.1-GB/s memory bandwidth, and 11.1-Mpolygon/s drawing speed, The 56-mm(2) prototype die integrating one edge processor, eight pixel processors, eight frame buffers, and a RISC core are fabricated using 0.35-mum CMOS embedded memory logic (EML) technology with four poly lavers and three metal layers, The fabricated test chip, 590 mW at 100-MHz 3.3-V operation, is demonstrated with a host PC through a PCI bridge. | - |
dc.language | English | - |
dc.language.iso | en_US | en |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | A 7.1-GB/s low-power rendering engine in 2-D array-embedded memory logic CMOS for portable multimedia system | - |
dc.type | Article | - |
dc.identifier.wosid | 000168887000009 | - |
dc.identifier.scopusid | 2-s2.0-0035368865 | - |
dc.type.rims | ART | - |
dc.citation.volume | 36 | - |
dc.citation.issue | 6 | - |
dc.citation.beginningpage | 944 | - |
dc.citation.endingpage | 955 | - |
dc.citation.publicationname | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.embargo.liftdate | 9999-12-31 | - |
dc.embargo.terms | 9999-12-31 | - |
dc.contributor.localauthor | Yoo, Hoi-Jun | - |
dc.contributor.nonIdAuthor | Park, YH | - |
dc.contributor.nonIdAuthor | Han, SH | - |
dc.contributor.nonIdAuthor | Lee, JH | - |
dc.type.journalArticle | Article | - |
dc.subject.keywordAuthor | embedded memory | - |
dc.subject.keywordAuthor | embedded logic | - |
dc.subject.keywordAuthor | 3-D graphic rendering | - |
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