DC Field | Value | Language |
---|---|---|
dc.contributor.author | Woo, RC | ko |
dc.contributor.author | Choi, SD | ko |
dc.contributor.author | Sohn, JH | ko |
dc.contributor.author | Song, SJ | ko |
dc.contributor.author | Bae, YD | ko |
dc.contributor.author | Yoo, Hoi-Jun | ko |
dc.date.accessioned | 2008-07-22T05:02:08Z | - |
dc.date.available | 2008-07-22T05:02:08Z | - |
dc.date.created | 2012-02-06 | - |
dc.date.created | 2012-02-06 | - |
dc.date.issued | 2004-07 | - |
dc.identifier.citation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.39, pp.1101 - 1109 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.uri | http://hdl.handle.net/10203/6249 | - |
dc.description.abstract | A low-power three-dimensional (3-D) rendering engine with two texture units and 29-Mb embedded DRAM is designed and integrated into an LSI for mobile third-generation (3G) multimedia terminals. Bilinear MIPMAP texture-mapped 3-D graphics can be realized with the help of low-power pipeline structure, optimization of datapath, extensive clock gating, texture address alignment, and the distributed activation of embedded DRAM. The scalable performance reaches up to 100 Mpixels/s and 400 Mtexels/s at 50 MHz. The chip is implemented with 0.16-mum pure DRAM process to reduce the fabrication cost of the embedded-DRAM chip. The logic with DRAM takes 46 mm(2) and consumes 140 mW at 33-MHz operation, respectively. The 3-D graphics images are successfully demonstrated by using the fabricated chip on the prototype PDA board. | - |
dc.language | English | - |
dc.language.iso | en_US | en |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | A low-power 3-D rendering engine with two texture units and 29-Mb embedded DRAM for 3G multimedia terminals | - |
dc.type | Article | - |
dc.identifier.wosid | 000222279700013 | - |
dc.identifier.scopusid | 2-s2.0-3042786045 | - |
dc.type.rims | ART | - |
dc.citation.volume | 39 | - |
dc.citation.beginningpage | 1101 | - |
dc.citation.endingpage | 1109 | - |
dc.citation.publicationname | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.identifier.doi | 10.1109/JSSC.2004.829406 | - |
dc.embargo.liftdate | 9999-12-31 | - |
dc.embargo.terms | 9999-12-31 | - |
dc.contributor.localauthor | Yoo, Hoi-Jun | - |
dc.contributor.nonIdAuthor | Woo, RC | - |
dc.contributor.nonIdAuthor | Choi, SD | - |
dc.contributor.nonIdAuthor | Sohn, JH | - |
dc.contributor.nonIdAuthor | Song, SJ | - |
dc.contributor.nonIdAuthor | Bae, YD | - |
dc.type.journalArticle | Article; Proceedings Paper | - |
dc.subject.keywordAuthor | embedded DRAM | - |
dc.subject.keywordAuthor | low power | - |
dc.subject.keywordAuthor | mobile application | - |
dc.subject.keywordAuthor | PDA | - |
dc.subject.keywordAuthor | portable | - |
dc.subject.keywordAuthor | texture mapping | - |
dc.subject.keywordAuthor | 3-D graphics rendering | - |
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