An energy-efficient analog front-end circuit for a sub-1-V digital hearing aid chip

Abstract

A low-power energy-efficient adaptive analog front-end circuit is proposed and implemented for digital hearing-aid applications. It adopts the combined-gain-control (CGC) technique for accurate preamplification and the adaptive-SNR (ASNR) technique to improve dynamic range with low power consumption. The CGC technique combines an automatic gain control and an exponential gain control together to reduce power dissipation and to control both gain and threshold knee voltage. The ASNR technique changes the value of the signal-to-noise ratio (SNR) in accordance with input amplitude in order to minimize power consumption and to optimize the SNR by sensing an input signal. The proposed analog front-end circuit achieves 86-dB peak SNR in the case of third-order EA modulator with 3.8-mu Vrms of input-referred noise voltage. It dissipates a minimum and maximum power of 59.4 and 74.7 mu W, respectively, at a single 0.9-V supply. The core area is 0.5 mm(2) in a 0.25-mu m standard CMOS technology.