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NO | Title, Author(s) (Publication Title, Volume Issue, Page, Issue Date) |
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Memory-Augmented Convolutional Neural Networks With Triplet Loss for Imbalanced Wafer Defect Pattern Classification Hyun, Yunseung; Kim, Heeyoung, IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, v.33, no.4, pp.622 - 634, 2020-11 | |
Variational Deep Clustering of Wafer Map Patterns Hwang, Jonghyun; Kim, Heeyoung, IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, v.33, no.3, pp.466 - 475, 2020-08 | |
Prediction of Highly Imbalanced Semiconductor Chip-Level Defects in Module Tests Using Multimodal Fusion and Logit Adjustment Cho, Hunsung; Koo, Wonmo; Kim, Heeyoung, IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, v.36, no.3, pp.425 - 433, 2023-08 |
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