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College of Engineering(공과대학)School of Electrical Engineering(전기및전자공학부)EE-Conference Papers(학술회의논문)

Implementation of low jitter clock distribution using chip-package hybrid interconnection

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dc.contributor.authorRyu, C.ko
dc.contributor.authorChung, D.ko
dc.contributor.authorBae, K.ko
dc.contributor.authorYu, J.ko
dc.contributor.authorKim, Jounghoko
dc.date.accessioned2007-06-21T01:20:21Z-
dc.date.available2007-06-21T01:20:21Z-
dc.date.created2012-02-06-
dc.date.created2012-02-06-
dc.date.issued2004-10-25-
dc.identifier.citationIEEE 13th Topical Meeting on Electrical Performance of Electronic Packaging, pp.291 - 294-
dc.identifier.urihttp://hdl.handle.net/10203/588-
dc.languageEnglish-
dc.language.isoen_USen
dc.publisherIEEE-
dc.titleImplementation of low jitter clock distribution using chip-package hybrid interconnection-
dc.typeConference-
dc.identifier.wosid000225765800069-
dc.identifier.scopusid2-s2.0-15944396936-
dc.type.rimsCONF-
dc.citation.beginningpage291-
dc.citation.endingpage294-
dc.citation.publicationnameIEEE 13th Topical Meeting on Electrical Performance of Electronic Packaging-
dc.identifier.conferencecountryUS-
dc.identifier.conferencelocationPortland, OR-
dc.embargo.liftdate9999-12-31-
dc.embargo.terms9999-12-31-
dc.contributor.localauthorKim, Joungho-
dc.contributor.nonIdAuthorRyu, C.-
dc.contributor.nonIdAuthorChung, D.-
dc.contributor.nonIdAuthorBae, K.-
dc.contributor.nonIdAuthorYu, J.-
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EE-Conference Papers(학술회의논문)
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