A NEW HARDWARE-BASED FAULT-TOLERANT CLOCK SYNCHRONIZATION SCHEME FOR REAL-TIME MULTIPROCESSOR SYSTEMS

Abstract

Clock synchronization schemes in the presence of faults have been investigated extensively in recent years to increase reliability in real-time systems. Among the clock synchronization schemes, hardware-based clock synchronization scheme is preferable one for the time-critical applications that need tight and reliable clock synchronization. In this paper, we propose a new hardware-based clock synchronization scheme, which uses digital docks instead of analog phase-locked clocks. We replace a complex clock selection rule of the conventional hardware-based clock synchronization by a modified software-based clock synchronization algorithm with hardware implementation to remedy the problems of the conventional hardware-based one. A result for the maximum clock skew of the hardware-based synchronization is presented. Also, we present a method to reduce the number of interconnections of clock networks to half of the conventional one. The function of the proposed scheme is simulated in the presence of Byzantine faults by a hardware description language, Verilog.