A 13bit 2.5MHz Self-Calibrated Pipelined A/D Converter in 3um CMOS

Abstract

While most current video applications of A/D converters require 8 b of resolution, more advanced applications will require higher resolutions. Great progress has been made in achieving 10-b resolution at video rates for HDTV using multistep flash [1], [2] and pipeline architectures [3], [4]. However, certain applications such as wide dynamic range imaging require 12 b of resolution at video rates. Currently, such high-performance converters are usually implemented in hybrid technologies with precision discrete components and are very expensive. This paper describes a self-calibrated pipelined A/D converter technique potentially appropriate for such high-resolution video applications. This approach requires much less area than multistep flash approaches and requires fewer clock cycles than error averaging techniques [5]. Since self-calibration can be performed during interframe intervals, this approach is particularly attractive for video applications. A 3-mu-m CMOS prototype fabricated using this architecture achieves 13-b resolution at 2.5 Msample/s, consumes 100 mW, and occupies 40 kmil2 (26 mm2), with a single 5-V supply and two-phase nonoverlapping clock.