Analysis and simulation of multi processing architecture for the software based CCMP

Abstract

This thesis is composed of two topics. The first topic is regarding ``Analysis and Simulation of Multi Processing Architecture for the Software based CCMP.`` Multi-Processing System on a chip (MPSoC) is promising SoC integration technology to support the application which needs high computational performance with low power consumption. In MPSoC, deciding the hardware architecture and partitioning the software for parallel processing play an important role in determining the performance and complexity of MPSoC platform. In this thesis, the CTR with CBC-MAC protocol (CCMP) architecture for MPSoC is proposed. CCMP is security protocol in IEEE 802.11i, which requires iterative substitution, mixing, and key expansion for each frame. The throughput constraints make it impossible to be implemented by single processor. Thus, CCMP should be implemented by MPSoC to speed up the processing time. On the designed hard-ware architecture, the performance of efficient software based CCMP for MPSoC is simulated and the complexity of hardware architecture is analyzed. The Second topic is regarding “Power aware design for digital baseband of ISO/IEC 14443 Type B RFID Reader.” Low power Radio Frequency IDentification(RFID) reader is growing issue for ubiquitous society. The application of RFID is electronic payment, personal identification, and distribution system. Among these applications, 13.56MHz frequency RFID, which is standardized as ISO/IEC 14443 type A, type B, 15693 and 18000-3, is intended for smart card for electronic payment and personal identification for security. To integrate this RFID reader with other devices with small size battery, low power implementation of 13.56MHz RFID reader is important. In this thesis, design schemes for low power are applied into 13.56MHz RFID reader. Register Transfer Level (RTL) and gate level power optimization are applied for ISO/IEC 14443 Type B RFID reader. The power consumption of RFID reader after low power optimization is com...