Optimal layout for cross-connected transistors in high-frequency differential oscillators

Abstract

Recently, sharply increasing demand for the wireless communication applications accelerates research for high-frequency and wide-band wireless communication systems. Accordingly, high-frequency oscillator design is an issue due to its significant role in the wireless communication systems. First of all, in order to design high-frequency oscillators, high maximum oscillation frequency ($f_{max}$) and high Q-factor of inductors and capacitors should be obtained. However, in spite of its relatively low $f_{max}$, CMOS technology is preferable in the industry due to the advantages of low-cost, low-power, and easy integration. In this thesis, , an optimal cross-connected transistor layout for high-frequency differential oscillators is presented in CMOS process where $f_{max}$ and $f_{T}$ are relatively low. The proposed layout minimizes not only intrinsic parasitic components of active devices but also external parasitic components from compact layout of implementing the transistor-pair on a single transistor layout. Besides, two cross-connected transistors are perfectly symmetric due to its common-centroid structure, thereby free from the possible mismatch by process gradient. In terms of layout complexity and size, the proposed structure also shows relatively improved performance. Moreover, from the fact that the proposed layout is easily obtained with a simple modification of the standard transistor cell, it has possibility of being registered as a standard cell, resulting in wide-use in various area.