Design of multiplexer/demultiplexer integrated with bidirectional transceiver for chip-to-chip optical interconnects

Abstract

In the seen improvement of device technology, scaling down microprocessors are commercially available with a clock speed of more than 3.2 GHz for Intel Pentium 4 processor on 90 nm and 65 nm technologies, and through the reduction of feature size (now less than 30 nm) this speed has been progressively increasing along. All the connections, such as bus lines, in the computer systems are, meanwhile, based on conventional copper-based printedcircuit boards (PCBs) which have limited physical properties that are hard to meet the demand in the gigahertz systems. The increases in both clock speed and number of connections have challenged at the conventional copper-based PCB in usage as chip-to-chip interconnects and stimulated a shift to the potential optical interconnects. In this thesis, a novel single chip architecture for bidirectional optical interconnects has been proposed and designed. For the bidirectional single chip, fundamental blocks of the chip have been first designed and simulated, and integrated into a single chip with controlling switches. These are a 4:1 multiplexer (MUX) with 10 Gb/s output, a 1:4 demultiplexer (DEMUX) with 10 Gb/s input, a 10 Gb/s optical transmitter (Tx), and a 10 Gb/s optical receiver (Rx). These are designed in the sense of unidirectional communication. In reality, however, chip-to-chip communication is bidirectional. This thesis proposes a single chip architecture including MUX/DEMUX integrated with bidirectional transceiver (Bi-TRx) instead of using two separated unidirectional chip sets at each side. Integrating MUX and DEMUX, Tx and Rx results in reducing power dissipation and chip area. The proposed single-chip operates in two working modes: MUX/Tx mode and Rx/DEMUX mode which are exchanged by a controlling signal. This new single chip architecture of MUX/DEMUX integrated with Bi-TRx has been simulated at 5 Gb/s and demonstrated excellent performance. The novel single chip proposed in this thesis will be applied for seri...