METASTABILITY OF CMOS LATCH FLIP-FLOP

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dc.contributor.authorKim, Lee-Supko
dc.contributor.authorDUTTON, RWko
dc.date.accessioned2007-06-07T01:07:52Z-
dc.date.available2007-06-07T01:07:52Z-
dc.date.created2012-02-06-
dc.date.created2012-02-06-
dc.date.issued1990-08-
dc.identifier.citationIEEE JOURNAL OF SOLID-STATE CIRCUITS, v.25, no.4, pp.942 - 951-
dc.identifier.issn0018-9200-
dc.identifier.urihttp://hdl.handle.net/10203/471-
dc.descriptionJSSC 1990en
dc.description.sponsorshipThe authors wish to thank Signetics for fabricating the test circuits. The authors also thank R. Cline of Signetics for helping with the measurements.en
dc.languageEnglish-
dc.language.isoen_USen
dc.publisherIEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC-
dc.titleMETASTABILITY OF CMOS LATCH FLIP-FLOP-
dc.typeArticle-
dc.identifier.wosidA1990DQ56300005-
dc.type.rimsART-
dc.citation.volume25-
dc.citation.issue4-
dc.citation.beginningpage942-
dc.citation.endingpage951-
dc.citation.publicationnameIEEE JOURNAL OF SOLID-STATE CIRCUITS-
dc.identifier.doi10.1109/4.58286-
dc.embargo.liftdate9999-12-31-
dc.embargo.terms9999-12-31-
dc.contributor.localauthorKim, Lee-Sup-
dc.contributor.nonIdAuthorDUTTON, RW-
dc.type.journalArticleArticle-
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