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| NO | Title, Author(s) (Publication Title, Volume Issue, Page, Issue Date) |
|---|---|
| A Dual-Shader 3-D Graphics Processor With Fast 4-D Vector Inner Product Units and Power-Aware Texture Cache Yoon, Jae-Sung; Yu, Chang-Hyo; Kim, Dong-Hyun; Kim, Lee-Sup, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.19, no.4, pp.525 - 537, 2011-04 | |
| DRAM-Latency Optimization Inspired by Relationship between Row-Access Time and Refresh Timing Shin, Wongyu; Choi, Jungwhan; Jang, Jaemin; Suh, Jinwoong; Moon, Youngsuk; Kwon, Yongkee; Kim, Lee-Sup, IEEE TRANSACTIONS ON COMPUTERS, v.65, no.10, pp.3027 - 3040, 2016-10 | |
| Refresh-Aware Write Recovery Memory Controller Jang, Jaemin; Shin, Wongyu; Choi, Jungwhan; Suh, Jinwoong; Kwon, Yongkee; Kim, Yongju; Kim, Lee-Sup, IEEE TRANSACTIONS ON COMPUTERS, v.66, no.4, pp.688 - 701, 2017-04 | |
| Q-DRAM: Quick-Access DRAM with Decoupled Restoring from Row-Activation Shin, Wongyu; Choi, Jung Whan; Jang, Jaemin; Suh, Jinwoong; Kwon, Yongkee; Moon, Youngsuk; Kim, Hongsik; Kim, Lee-Sup, IEEE TRANSACTIONS ON COMPUTERS, v.65, no.7, pp.2213 - 2227, 2016-07 |
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