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Results 1-10 of 17 (Search time: 0.008 seconds).

NO Title, Author(s) (Publication Title, Volume Issue, Page, Issue Date)
1
Effective Schottky Barrier Height Lowering of Metal/n-Ge with a TiO2/GeO2 Interlayer Stack

Kim, Gwang-Sik; Kim, Sun-Woo; Kim, Seung-Hwan; Park, June; Seo, Yujin; Cho, Byung-Jin; Shin, Changhwan; Shim, Jong Hyung; Yu, Hyun-Yong, ACS APPLIED MATERIALS INTERFACES, v.8, no.51, pp.35419 - 35425, 2016-12

2
High-Gain Wide-Bandwidth Capacitor-Less Low-Dropout Regulator (LDO) for Mobile Applications Utilizing Frequency Response of Multiple Feedback Loops

Hong, Sung Wan; Cho, Gyu-Hyeong, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.63, no.1, pp.46 - 57, 2016-01

3
Hybrid Integration of Graphene Analog and Silicon Complementary Metal-Oxide-Semiconductor Digital Circuits

Hong, Seul Ki; Kim, Choong Sun; Hwang, Wan Sik; Cho, Byung-Jin, ACS NANO, v.10, no.7, pp.7142 - 7146, 2016-07

4
A 79 pJ/b 80 Mb/s Full-Duplex Transceiver and a 42.5 mu W 100 kb/s Super-Regenerative Transceiver for Body Channel Communication

Cho, Hyunwoo; Kim, Hyunki; Kim, Minseo; Jang, Jaeeun; Lee, Yongsu; Lee, Kyuho Jason; Bae, Joonsung; Yoo, Hoi-Jun, IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.51, no.1, pp.310 - 317, 2016-01

5
Design and analysis of a multichannel transceiver for high-speed optical interconnects

Sangirov, Jamshid; Rakib-Uddin, Mohammad; Sangirov, Gulomjon; Ukaegbu, Ikechi Augustine; Nakarmi, Bikash; Lee, Tae-Woo; Park, Hyo-Hoon, OPTICAL AND QUANTUM ELECTRONICS, v.48, no.1, 2016-01

6
A 5-Gb/s 2.67-mW/Gb/s Digital Clock and Data Recovery With Hybrid Dithering Using a Time-Dithered Delta-Sigma Modulator

Lee, Taeho; Kim, Yonghun; Sim, Jaehyeong; Park, Jun-Seok; Kim, Lee-Sup, IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.24, no.4, pp.1450 - 1459, 2016-04

7
A D-Band Gain-Boosted Current Bleeding Down-Conversion Mixer in 65 nm CMOS for Chip-to-Chip Communication

Lee, Chae-Jun; Park, Chul Soon, IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, v.26, no.2, pp.143 - 145, 2016-02

8
A Sign-Equality-Based Background Timing-Mismatch Calibration Algorithm for Time-Interleaved ADCs

Kang, Hyun-Wook; Hong, Hyeok-Ki; Park, Sanghoon; Kim, Ki-Jin; Ahn, Kwang-Ho; Ryu, Seung-Tak, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, v.63, no.6, pp.518 - 522, 2016-06

9
A 109 GHz CMOS Power Amplifier With 15.2 dBm Psat and 20.3 dB Gain in 65-nm CMOS Technology

Son, Hyuk Su; Jang, Joo Young; Kang, Dong Min; Lee, Hae Jin; Park, Chul Soon, IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS, v.26, no.7, pp.510 - 512, 2016-07

10
Effect of Metal Nitride on Contact Resistivity of Metal-Interlayer-Ge Source/Drain in Sub-10-nm n-Type Ge FinFET

Ahn, Juhan; Kim, Jeong-Kyu; Kim, Sun-Woo; Kim, Gwang-Sik; Shin, Changhwan; Kim, Jong-Kook; Cho, Byung-Jin; Yu, Hyun-Yong, IEEE ELECTRON DEVICE LETTERS, v.37, no.6, pp.705 - 708, 2016-06

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