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NO | Title, Author(s) (Publication Title, Volume Issue, Page, Issue Date) |
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Modeling and verification of 3-dimensional resistive storage class memory with high speed circuits for core operation Son, Kyungjune; Cho, Kyungjun; Kim, Subin; Park, Shinyoung; Park, Gap Yeol; Kim, Seongguk; Shin, Taein; Kim, Joungho, 2019 IEEE Asia-Pacific Microwave Conference, APMC 2019, pp.694 - 696, Institute of Electrical and Electronics Engineers Inc., 2019-12 | |
Bayesian Optimization of High-Speed Channel for Signal Integrity Analysis Lho, Daehwan; Park, Junyong; Park, Hyunwook; Park, Shinyoung; Kim, SeongGuk; Kang, Hyungmin; Kim, Subin; Park, Gap Yeol; Son, Kyungjune; Kim, Joungho, 28th IEEE Conference on Electrical Performance of Electronic Packaging and Systems, EPEPS 2019, Institute of Electrical and Electronics Engineers Inc., 2019-10 | |
Modeling and analysis of multiple coupled through-silicon vias (TSVs) for 2.5-D/3-D ICs Cho, Kyungjun; Kim, Youngwoo; Park, Junyong; Kim, Hyesoo; Kim, Seongguk; Kim, Subin; Park, Gap Yeol; Son, Kyungjune; Kim, Joungho, Joint International Symposium on Electromagnetic Compatibility, Sapporo and Asia-Pacific International Symposium on Electromagnetic Compatibility, EMC Sapporo/APEMC 2019, pp.346 - 349, Institute of Electrical and Electronics Engineers Inc., 2019-06 |
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