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Showing results 1 to 6 of 6

1
A 5-Gb/s/pin transceiver for DDR memory interface with a crosstalk suppression scheme

Oh, K.-I.; Kim, Lee-Sup; Park, K.-I.; Jun, Y.-H.; Kim, K., IEEE 2008 Custom Integrated Circuits Conference, CICC 2008, pp.639 - 642, 2008-09-21

2
A 500MHz DLL with second order duty cycle corrector for low jitter

Kim, B.-G.; Oh, K.-I.; Kim, Lee-Sup; Lee, D.-W., IEEE 2005 Custom Integrated Circuits Conference, pp.318 - 321, IEEE, 2005-09-18

3
A Clock Delayed Sleep Mode Domino Logic for Wide Dynamic OR Gate

Oh, K.-I.; Kim, Lee-Sup, Proceedings of the 2003 International Symposium on Low Power Electronics and Design, (ISLPED'03), pp.176 - 179, 2003-08-25

4
A high performance low power dynamic PLA with conditional evaluation scheme

Oh, K.-I.; Kim, Lee-Sup, 2004 IEEE International Symposium on Cirquits and Systems - Proceedings, IEEE, 2004-05-23

5
A low power SoC bus with low-leakage and low-swing technique

Oh, K.-I.; Cho, S.; Kim, Lee-Sup, ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems, pp.1019 - 1022, IEEE, 2006-05-21

6
Cancelation of a crosstalk induced noise in a DDR memory interface

Oh, K.-I.; Kim, Lee-Sup; Park, K.-I.; Jun, Y.-H.; Kim, K., 2008 International SoC Design Conference, ISOCC 2008, 123, 2008-11-24

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