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A Two-step 5b Logarithmic ADC with Minimum Step-size of 0.1% Full-scale for MLC Phase-Change Memory Readout

Kwon, JW; Jin, DH; Kim, HJ; Hwang, SI; Shin, MC; Kang, JH; Ryu, Seung-Tak, Custom Integrated Circuits Conference(CICC), IEEE, 2014-09-17

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