Showing results 1 to 4 of 4
A Mask Reuse Methodology for Reducing System-on-a-Chip Cost Bhattacharya, S; Darringer, J; Ostapko, D; Shin, Youngsoo, Sixth International Symposium on Quality Electronic Design, pp.482 - 487, IEEE, 2005-03 |
Modeling and analysis of power for System-on-a-Chip design Nair, I.I.; Shin, Youngsoo; Bergamaschi, R.A.; Bhattacharya, S; Darringer, J; Kosonocky, S, IBM Austin Conference on Energy-Efficient Design (ACEED), IBM, 2003-03 |
SEAS: a system for early analysis of SoCs Bergamaschi, R.A.; Shin, Youngsoo; Dhanwada, N; Bhattacharya, S; Dougherty, W.E.; Nair, I.I.; Darringer, J; et al, Int'l Conf. on Hardware/Software Codesign and System Synthesis, pp.150 - 155, ACM Press, 2003-10 |
Simultaneous exploration of power, physical design, and architectural performance dimensions of SoC design space using SEAS Dhanwada, N.; Bergamaschi, R.; Dungan, W.; Nair, I.; Dougherty, W.; Shin, Youngsoo; Bhattacharya, S.; et al, IP Based SoC Design Forum & Exhibition (IP-SoC), 2004-12 |
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