Browse "EE-Conference Papers(학술회의논문)" by Author 심성보
Showing results 1 to 3 of 3
| Full-chip level estimation of temperature-dependent leakage power 최수형; 심성보; 신영수, 한국반도체학술대회, 대한전자공학회, 2017-02-15 |
| Identifying redundant inter-cell margins and its application to technology mapping 이유종; 심성보; 신영수, 한국반도체학술대회, 대한전자공학회, 2014-02-25 |
| Reducing routing congestion and chip area by post placement optimization utilizing redundant inter-cell margin 정우현; 심성보; 신영수, 한국반도체학술대회, 대한전자공학회, 2015-02-10 |
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