(A) performance analysis and evaluation of a fast locking time All-Digital PLL

Abstract

In this thesis, we evaluate and analyze of the All-Digital Phase Locked Loop (ADPLL). We mention about metastability problems from the retiming logic and time-to-digital converter (TDC) in the ADPLL, and we suggest a solution to solve the metastability problem in the retiming logic. The VERILOG HDL language is used to simulate and verify the proposed retiming logic. The main object of this thesis is performance analysis and evaluation of the locking time in the ADPLL. The previously suggested ADPLL for fast locking time is explained and simulated in this thesis. The previous ADPLL is compared with our proposed ADPLL. Our proposed ADPLL uses a lookup-table for fast locking time. Because the temperature varies with time, a DCO’s LC tank chip is designed to analyze the temperature effect on the DCO. Even if the proposed ADPLL has phase-error due to temperature variation, it is possible to lock the proposed ADPLL within 1 reference cycle.