Development of a simulator for packet communication networks

Abstract

In this thesis a network simulator for packet communication network has been developed, which can handle voice and data packets. The main feature of the simulator is precise modeling of node processors. Considering the packet mode service and the hardware structure of a node processor, the packet network has been modeled using some queueing models. If input parameters such as traffic matrix are specified, the stepwise delays, utilizations and throughput of each module can be simulated. For solving memory problems in large-scale simulation, a hybrid analytic/simulation technique has been studied and used in the simulator implementation. Using the hybrid technique, significant improvements in the run time efficiency have been obtained, and some results using the technique have been shown. Parts of the results have been validated using some queueing theories, confirming that the simulator produces accurate results to a certain degree.