(A) design and VLSI implementation of pipeline merge sorter

Abstract

Sorting is a very frequently requested operation in data processing. Reflecting the recent development of VLSI technology, there is an increasing interest in specialized hardware sorter. By use of parallelism, O(N) time complexity hardware sorters are feasible. In this thesis, we deal with design and VLSI implementation of pipeline merge sorter, abbreviated PMS which uses the 2-way merge algorithm. The algorithm and architectural specification are presented. The functionality of our PMS is fully simulated with GENESIL, the silicon compiler that generates layout from the behavioral description. The layout of PMS is generated with CMOS 2$\mu$ n-well process technology, and the size of the chip is $9.4\times9.1 mm^2$. The timing analysis indicates its data rate is about 4 Mbytes/sec. We present the employment of the hardware sorter in data base management system has a good time save effect.