Design and fabrication of metal gate CMOS gate array(GA1.0)

Abstract

In this thesis, a metal gate CMOS Gate Array, named GA1.0, which contains 12 I/O cells and 15 array cells is designed and fabricated. In order to extract the electrical parameters of metal gate CMOS process, CMOS test patterns were fabricated and the model parameters of CMOS which is compatible with SPICE Level 11 MOS transistor model, were extracted. To measure the performance of GA1.0, 11 stage ring oscillator, 9 stage inverter chain and some other circuits were implemented in GA1.0 base. The immunity of the latch-ups were measured by transistor curve tracer. The latch-up occurs with 13 V of supply voltage and snap back to 3 V. The measured input undershoot triggering current (-80 mA) is much smaller than overshoot current (800 mA), which seems to be caused by insufficient $n^+$ guard. The output triggering currents are also measured to be ±40 mA. The switching voltage of array cell and I/O cell inverters are 1.85 and 2.05 V respectively, which agree well with SPICE simulation results. The measured delay times of the array cell from ring oscillator is 41 nsec, which also coincides well with SPICE simulation.